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11. 发明申请

US20070238314A1 System and process for producing nanowire composites and electronic substrates therefrom 有权
标题翻译：用于生产纳米线复合材料和电子基材的系统和工艺
公开(公告)号：US20070238314A1
公开(公告)日：2007-10-11
申请号：US11225951
申请日：2005-09-14
申请人： Mihai Buretea , Jian Chen , Calvin Chow , Chunming Niu , Yaoling Pan , J. Parce , Linda Romano , David Stumbo
发明人： Mihai Buretea , Jian Chen , Calvin Chow , Chunming Niu , Yaoling Pan , J. Parce , Linda Romano , David Stumbo
IPC分类号： H01L21/31
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/42384 , H01L29/66742 , H01L29/78681 , H01L29/78696 , H01L33/06 , H01L33/24 , H01L51/0048 , H01L51/0545 , H01L2924/0002 , Y10T428/2913 , H01L2924/00
摘要： The present invention relates to a system and process for producing a nanowire-material composite. A substrate having nanowires attached to a portion of at least one surface is provided. A material is deposited over the portion to form the nanowire-material composite. The process further optionally comprises separating the nanowire-material composite from the substrate to form a freestanding nanowire-material composite. The freestanding nanowire material composite is optionally further processed into a electronic substrate. A variety of electronic substrates can be produced using the methods described herein. For example, a multi-color light-emitting diode can be produced from multiple, stacked layers of nanowire-material composites, each composite layer emitting light at a different wavelength.
摘要翻译：本发明涉及纳米线材料复合体的制造方法和制造方法。提供了具有连接到至少一个表面的一部分的纳米线的衬底。在该部分上沉积材料以形成纳米线材料复合材料。该方法进一步任选地包括从衬底分离纳米线材料复合物以形成独立的纳米线材料复合材料。独立的纳米线材料复合材料任选进一步加工成电子基片。可以使用本文所述的方法来生产各种电子基板。例如，多个发光二极管可以由多个层叠的纳米线材料复合体制成，每个复合层发射不同波长的光。

12. 发明申请

US20060214156A1 Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires 失效
标题翻译：用于制造基于导电聚合物和半导体纳米线的塑料电子器件的完全集成的有机分层工艺
公开(公告)号：US20060214156A1
公开(公告)日：2006-09-28
申请号：US11233503
申请日：2005-09-22
申请人： Yaoling Pan , Francisco Leon , David Stumbo
发明人： Yaoling Pan , Francisco Leon , David Stumbo
IPC分类号： H01L29/08
CPC分类号： H01L51/0545 , B82Y10/00 , H01L29/0673 , H01L29/068 , H01L29/78681 , H01L29/7869 , H01L29/78696 , H01L51/0035 , H01L51/0037 , H01L51/0048 , H01L51/0049 , H01L51/0541 , H01L51/0566 , H01L51/4253 , H01L51/4266 , Y02E10/549 , Y02P70/521 , Y10S977/762 , Y10S977/763 , Y10S977/764
摘要： The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.
摘要翻译：本发明涉及使用并入和/或设置在导电聚合物层附近的纳米线（或诸如纳米带，纳米管等的其它纳米结构）的薄膜晶体管，以及用于生产这种晶体管的生产可扩展方法。特别地，公开了包含导电聚合材料如聚苯胺（PANI）或聚吡咯（PPY）和一个或多个纳米线的复合材料，其中并入其中。还提供了几种纳米线TFT制造方法，其在一个示例性实施例中包括提供器件衬底; 在器件衬底上沉积第一导电聚合物材料层; 限定所述导电聚合物层中的一个或多个栅极接触区域; 在所述导电聚合物层上以足够的纳米线密度沉积多个纳米线以实现工作电流水平; 在所述多个纳米线上沉积第二导电聚合物材料层; 以及在所述第二导电聚合物材料层中形成源极和漏极接触区域，从而提供与所述多个纳米线的电连接性，由此所述纳米线形成在所述源极和漏极区域中的相应长度之间具有长度的沟道。

13. 发明申请

US20060234519A1 Contact doping and annealing systems and processes for nanowire thin films 失效
标题翻译：接触纳米线薄膜的掺杂和退火系统和工艺
公开(公告)号：US20060234519A1
公开(公告)日：2006-10-19
申请号：US11271488
申请日：2005-11-10
申请人： Yaoling Pan , David Stumbo
发明人： Yaoling Pan , David Stumbo
IPC分类号： H01L21/00
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/66439 , H01L29/66469 , H01L29/66742 , H01L29/66772 , H01L29/7606 , H01L29/78696 , Y10S977/901 , Y10S977/963
摘要： Embodiments of the present invention are provided for improved contact doping and annealing systems and processes. In embodiments, a plasma ion immersion implantation (PIII) process is used for contact doping of nanowires and other nanoelement based thin film devices. According to further embodiments of the present invention, pulsed laser annealing using laser energy at relatively low laser fluences below about 100 mJ/cm2 (e.g., less than about 50 mJ/cm2, e.g., between about 2 and 18 mJ/cm2) is used to anneal nanowire and other nanoelement-based devices on substrates, such as low temperature flexible substrates, e.g., plastic substrates.
摘要翻译：提供本发明的实施例用于改进的接触掺杂和退火系统和工艺。在实施例中，等离子体离子浸没注入（PIII）工艺用于纳米线和其它基于纳米元件的薄膜器件的接触掺杂。根据本发明的另外的实施例，使用在低于约100mJ / cm 2（例如小于约50mJ / cm 2）的较低激光能量密度的激光能量进行脉冲激光退火， SUP>，例如约2和18mJ / cm 2之间）用于退火衬底上的纳米线和其它基于纳米元件的器件，例如低温柔性衬底，例如塑料衬底。

14. 发明申请

US20080038520A1 Methods for oriented growth of nanowires on patterned substrates 有权
公开(公告)号：US20080038520A1
公开(公告)日：2008-02-14
申请号：US11641939
申请日：2006-12-20
申请人： Yaoling Pan , Xiangfeng Duan , Robert Dubrow , Jay Goldman , Shahriar Mostarshed , Chunming Niu , Linda Romano , David Stumbo , Alice Fischer-Colbrie , Vijendra Sahi , Virginia Robbins
发明人： Yaoling Pan , Xiangfeng Duan , Robert Dubrow , Jay Goldman , Shahriar Mostarshed , Chunming Niu , Linda Romano , David Stumbo , Alice Fischer-Colbrie , Vijendra Sahi , Virginia Robbins
IPC分类号： B32B15/02 , B05D5/12
CPC分类号： C30B29/605 , B82Y30/00 , C30B11/12 , C30B29/06 , Y10T428/24917
摘要： The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors, as well as us of patterned substrates to grow oriented nanowires. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrifical growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.

15. 发明申请

US20070187768A1 Nano-Enabled Memory Devices and Anisotropic Charge Carrying Arrays 有权
标题翻译：具有纳米功能的存储器件和各向异性电荷携带阵列
公开(公告)号：US20070187768A1
公开(公告)日：2007-08-16
申请号：US11695728
申请日：2007-04-03
申请人： Xiangfeng Duan , Calvin Chow , David Heald , Chunming Niu , J. Parce , David Stumbo
发明人： Xiangfeng Duan , Calvin Chow , David Heald , Chunming Niu , J. Parce , David Stumbo
IPC分类号： H01L29/94
CPC分类号： H01L21/28273 , B82Y10/00 , G03G5/00 , G03G5/02 , G03G5/04 , G03G5/043 , G03G5/08 , G03G5/082 , G03G5/08214 , G11C11/56 , G11C13/02 , G11C13/025 , G11C2213/17 , G11C2213/18 , G11C2216/08 , H01L29/42332 , H01L29/7881 , H01L29/7887 , Y10S977/774 , Y10S977/785 , Y10S977/936
摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.
摘要翻译：描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米的群体包括金属量子点。隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。在纳米元件的薄膜上形成栅极接触。纳米元件允许减少横向电荷转移。存储器件可以是单个或多个存储器件。在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了一种用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。

16. 发明申请

US20080026532A1 Nano-Enabled Memory Devices and Anisotropic Charge Carrying Arrays 审中-公开
标题翻译：具有纳米功能的存储器件和各向异性电荷携带阵列
公开(公告)号：US20080026532A1
公开(公告)日：2008-01-31
申请号：US11850127
申请日：2007-09-05
申请人： Xiangfeng Duan , Calvin Chow , David Heald , Chunming Niu , J. Parce , David Stumbo
发明人： Xiangfeng Duan , Calvin Chow , David Heald , Chunming Niu , J. Parce , David Stumbo
IPC分类号： H01L21/336
CPC分类号： H01L29/7887 , B82Y10/00 , G03G5/00 , G03G5/02 , G03G5/04 , G03G5/043 , G03G5/08 , G03G5/082 , G03G5/08214 , G11C11/56 , G11C13/02 , G11C13/025 , G11C2213/17 , G11C2213/18 , G11C2216/08 , H01L29/40114 , H01L29/42332 , H01L29/7881 , Y10S977/774 , Y10S977/785 , Y10S977/936
摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.
摘要翻译：描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米的群体包括金属量子点。隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。在纳米元件的薄膜上形成栅极接触。纳米元件允许减少横向电荷转移。存储器件可以是单个或多个存储器件。在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了一种用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。

17. 发明申请

US20070247904A1 Nano-enabled memory devices and anisotropic charge carrying arrays 审中-公开
标题翻译：具有纳米功能的存储器件和各向异性带电载体阵列
公开(公告)号：US20070247904A1
公开(公告)日：2007-10-25
申请号：US11766980
申请日：2007-06-22
申请人： Xiangfeng Duan , Calvin Chow , David Heald , Chunming Niu , J. Parce , David Stumbo
发明人： Xiangfeng Duan , Calvin Chow , David Heald , Chunming Niu , J. Parce , David Stumbo
IPC分类号： G11C16/04
CPC分类号： H01L29/7887 , B82Y10/00 , G03G5/00 , G03G5/02 , G03G5/04 , G03G5/043 , G03G5/08 , G03G5/082 , G03G5/08214 , G11C11/56 , G11C13/02 , G11C13/025 , G11C2213/17 , G11C2213/18 , G11C2216/08 , H01L29/40114 , H01L29/42332 , H01L29/7881 , Y10S977/774 , Y10S977/785 , Y10S977/936
摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.
摘要翻译：描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米的群体包括金属量子点。隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。在纳米元件的薄膜上形成栅极接触。纳米元件允许减少横向电荷转移。存储器件可以是单个或多个存储器件。在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了一种用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。

18. 发明申请

US20050201149A1 Nano-enabled memory devices and anisotropic charge carrying arrays 有权
标题翻译：具有纳米功能的存储器件和各向异性带电载体阵列
公开(公告)号：US20050201149A1
公开(公告)日：2005-09-15
申请号：US11018572
申请日：2004-12-21
申请人： Xiangfeng Duan , Calvin Chow , David Heald , Chunming Niu , J. Parce , David Stumbo
发明人： Xiangfeng Duan , Calvin Chow , David Heald , Chunming Niu , J. Parce , David Stumbo
IPC分类号： G11C16/04 , H01L21/28 , H01L29/423 , H01L29/788
CPC分类号： G11C11/56 , B82Y10/00 , G03G5/00 , G03G5/02 , G03G5/04 , G03G5/043 , G03G5/08 , G03G5/082 , G03G5/08214 , G11C13/02 , G11C13/025 , G11C2213/17 , G11C2213/18 , G11C2216/08 , H01L21/28273 , H01L21/28282 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/42332 , H01L29/7881 , H01L29/7887 , Y10S977/936 , Y10S977/943
摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.
摘要翻译：描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米的群体包括金属量子点。隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。在纳米元件的薄膜上形成栅极接触。纳米元件允许减少横向电荷转移。存储器件可以是单个或多个存储器件。在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了一种用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。

19. 发明申请

US20070012980A1 Large-area nanoenabled macroelectronic substrates and uses therefor 有权
公开(公告)号：US20070012980A1
公开(公告)日：2007-01-18
申请号：US11490637
申请日：2006-07-21
申请人： Xiangfeng Duan , Chunming Niu , Stephen Empedocles , Linda Romano , Jian Chen , Vijendra Sahi , Lawrence Bock , David Stumbo , J. Parce , Jay Goldman
发明人： Xiangfeng Duan , Chunming Niu , Stephen Empedocles , Linda Romano , Jian Chen , Vijendra Sahi , Lawrence Bock , David Stumbo , J. Parce , Jay Goldman
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L29/0665 , B82Y10/00 , H01F1/405 , H01L27/092 , H01L27/12 , H01L27/1292 , H01L29/0673 , H01L29/068 , H01L29/78696 , H01L31/035281 , H01L33/18 , H01L33/20 , H01L33/24 , H01L51/0048 , H01L51/0504 , H01L51/0545 , H01L51/0595 , Y10S977/742 , Y10S977/762 , Y10S977/781 , Y10S977/789 , Y10S977/938
摘要： A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.

20. 发明授权

US07932511B2 Large-area nanoenabled macroelectronic substrates and uses therefor 有权
标题翻译：大面积纳米大电子基板及其用途
公开(公告)号：US07932511B2
公开(公告)日：2011-04-26
申请号：US11681058
申请日：2007-03-01
申请人： Xiangfeng Duan , Chunming Niu , Stephen Empedocles , Linda T. Romano , Jian Chen , Vijendra Sahi , Lawrence Bock , David Stumbo , J. Wallace Parce , Jay L. Goldman
发明人： Xiangfeng Duan , Chunming Niu , Stephen Empedocles , Linda T. Romano , Jian Chen , Vijendra Sahi , Lawrence Bock , David Stumbo , J. Wallace Parce , Jay L. Goldman
IPC分类号： H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , H01F1/405 , H01L27/092 , H01L27/12 , H01L27/1292 , H01L29/0673 , H01L29/068 , H01L29/78696 , H01L31/035281 , H01L33/18 , H01L33/20 , H01L33/24 , H01L51/0048 , H01L51/0504 , H01L51/0545 , H01L51/0595 , Y10S977/742 , Y10S977/762 , Y10S977/781 , Y10S977/789 , Y10S977/938
摘要： A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.
摘要翻译：描述了具有多个半导体器件的电子基片的方法和装置。在衬底上形成纳米线薄膜。纳米线的薄膜形成为具有足够的纳米线密度以达到工作电流水平。在纳米线的薄膜中限定多个半导体区域。在半导体器件区域处形成触点，从而提供与多个半导体器件的电连接。此外，用于制造纳米线的各种材料，包括p掺杂纳米线和n掺杂纳米线的薄膜，纳米线异质结构，发光纳米线异质结构，用于在衬底上定位纳米线的流动掩模，用于沉积纳米线的纳米线喷涂技术，用于减少或消除声子的技术描述了纳米线中的电子散射，以及用于降低纳米线中的表面状态的技术。

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