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11. 发明授权

US06944090B2 Method and circuit for precise timing of signals in an embedded DRAM array 失效
标题翻译：用于嵌入式DRAM阵列中信号精确定时的方法和电路
公开(公告)号：US06944090B2
公开(公告)日：2005-09-13
申请号：US10604184
申请日：2003-06-30
申请人： Darren L. Anand , John A. Fifield , Harold Pilo
发明人： Darren L. Anand , John A. Fifield , Harold Pilo
IPC分类号： G11C29/02 , G11C8/00
CPC分类号： G11C29/50012 , G11C11/401 , G11C29/02 , G11C2029/0401 , G11C2029/1204
摘要： A method and circuit for timing the start of a precharge period in an eDRAM. The circuit including: a delayed lock loop circuit for receiving a clock signal and generating a control signal for adjusting an internal delay of the clock signal; and means for generating a delayed clock signal in response to the control signal. The means for generating the delayed clock signal is a multiple stage delay circuit, each stage of the multiple delay stage circuit connected in series and each stage individually responsive to the control signal.
摘要翻译：一种用于定时在eDRAM中预充电期间开始的方法和电路。该电路包括：延迟锁定环电路，用于接收时钟信号并产生用于调整时钟信号的内部延迟的控制信号; 以及用于响应于控制信号产生延迟的时钟信号的装置。用于产生延迟时钟信号的装置是多级延迟电路，多级延迟级电路的每级串联连接，每级分别响应控制信号。

12. 发明申请

US20080155151A1 Programmable Locking Mechanism For Secure Applications In An Integrated Circuit 审中-公开
标题翻译：可编程锁定机制，用于集成电路中的安全应用
公开(公告)号：US20080155151A1
公开(公告)日：2008-06-26
申请号：US11615137
申请日：2006-12-22
申请人： John A. Fifield , Steven F. Oakland , Michael R. Ouellette
发明人： John A. Fifield , Steven F. Oakland , Michael R. Ouellette
IPC分类号： G06F21/00
CPC分类号： G06K19/073 , G06K19/07309
摘要： A programmable locking mechanism for use in an integrated circuit is disclosed. In particular, the programmable locking mechanism may include an access code storage circuit for storing a security access code and a code input register whose outputs feed a comparator circuit that generates a locking signal. The state of the locking signal depends on whether the contents of the access code storage circuit and the code input register match. Additionally, a blocking circuit is provided that interrupts a programming input to the access code storage circuit and, thus, allows or denies access via the programming input to the access code storage circuit depending on the state of the locking signal. Additionally, the locking signal is distributed to sensitive logic circuits within the integrated circuit for preventing and/or allowing (depending on state) access thereto.
摘要翻译：公开了一种用于集成电路的可编程锁定机构。特别地，可编程锁定机构可以包括用于存储安全访问代码的访问代码存储电路和其输出馈送产生锁定信号的比较器电路的代码输入寄存器。锁定信号的状态取决于访问代码存储电路和代码输入寄存器的内容是否匹配。此外，提供一种阻塞电路，其中断对访问代码存储电路的编程输入，并且因此根据锁定信号的状态允许或拒绝通过对访问代码存储电路的编程输入的访问。此外，锁定信号被分配到集成电路内的敏感逻辑电路，用于防止和/或允许（取决于状态）对其的访问。

13. 发明授权

US08724365B2 Programmable semiconductor device 有权
标题翻译：可编程半导体器件
公开(公告)号：US08724365B2
公开(公告)日：2014-05-13
申请号：US13427162
申请日：2012-03-22
申请人： William R. Tonti , Wayne S. Berry , John A. Fifield , William H. Guthrie , Richard S. Kontra
发明人： William R. Tonti , Wayne S. Berry , John A. Fifield , William H. Guthrie , Richard S. Kontra
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
摘要翻译：可编程器件包括衬底（10）; 绝缘体（13）; 绝缘体上的细长半导体材料（12），具有第一和第二端的细长半导体材料和上表面S; 第一端部（12a）比第二端部（12b）大得多，金属材料设置在上表面上; 所述金属材料可响应于流过半导体材料和金属材料的电流I而沿着上表面物理迁移。

14. 发明申请

US20140003164A1 MEMORY ARRAY WITH ON AND OFF-STATE WORDLINE VOLTAGES HAVING DIFFERENT TEMPERATURE COEFFICIENTS 有权
标题翻译：具有开启和关闭状态的存储器阵列具有不同温度系数的字线电压
公开(公告)号：US20140003164A1
公开(公告)日：2014-01-02
申请号：US13534096
申请日：2012-06-27
申请人： John A. Fifield , Mark D. Jacunski
发明人： John A. Fifield , Mark D. Jacunski
IPC分类号： G11C5/14 , H02J1/10 , G11C8/08
CPC分类号： G11C8/08 , G11C7/04 , G11C11/4085 , Y10T307/555
摘要： Disclosed is a memory array structure, where a wordline driver selectively applies a high on-state voltage (VWLH) or a low off-state voltage (VWLL) to a wordline. VWLH has a slightly negative temperature coefficient so that it is regulated as high as the gate dielectric reliability limits allow, whereas VWLL has a substantially neutral temperature coefficient. To accomplish this, the wordline driver is coupled to one or more voltage regulation circuits. In one embodiment, the wordline driver is coupled to a single voltage regulation circuit, which incorporates a single voltage reference circuit having a single output stage that outputs multiple reference voltages. Also disclosed is a voltage reference circuit, which can be incorporated into the voltage regulation circuit of a memory array structure, as described, or, alternatively, into any other integrated circuit structure requiring voltages with different temperature coefficients. Also disclosed is a method of operating a memory array structure.
摘要翻译：公开了一种存储器阵列结构，其中字线驱动器选择性地将高导通状态电压（VWLH）或低关态电压（VWLL）施加到字线。 VWLH具有轻微的负温度系数，使得其受到栅极介电可靠性限制允许的高度调节，而VWLL具有基本上中性的温度系数。为了实现这一点，字线驱动器耦合到一个或多个电压调节电路。在一个实施例中，字线驱动器耦合到单个电压调节电路，其包括具有输出多个参考电压的单个输出级的单个电压参考电路。还公开了一种电压参考电路，其可以结合到如所描述的存储器阵列结构的电压调节电路中，或者可以并入任何其它需要具有不同温度系数的电压的集成电路结构。还公开了一种操作存储器阵列结构的方法。

15. 发明授权

US08027207B2 Leakage compensated reference voltage generation system 有权
标题翻译：泄漏补偿参考电压发生系统
公开(公告)号：US08027207B2
公开(公告)日：2011-09-27
申请号：US12639454
申请日：2009-12-16
申请人： John A. Fifield , Harold Pilo
发明人： John A. Fifield , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C17/16 , G11C5/147 , G11C7/062 , G11C7/12 , G11C17/18 , G11C29/02 , G11C29/021 , G11C29/028
摘要： An e-fuse sense circuit employs a single ended sense scheme in which the reference voltage is compensated for leakage. A reference voltage generator includes a pull-up resistor of similar value to the selected bitline pull-up resistor. As the sensing trip point is adjusted by selection of a bitline pull-up resistor, a pair of pull-up and pull-down resistors are adjusted together to adjust the impedance of the reference voltage generator. A leakage-path simulation structure including a parallel connection of bitcells is added to the reference voltage generator. The leakage-path simulation structure imitates the bitcells on a bitline in the array of e-fuses. Leakage current on the bitline offsets the bitline voltage by a certain error voltage. The reference voltage is also offset by a fraction of the error voltage to balance the shifts in the ‘1’ and ‘0’ margin levels in the presence of leakage.
摘要翻译：电熔丝感测电路采用单端感测方案，其中参考电压被补偿以进行泄漏。参考电压发生器包括与所选位线上拉电阻相似的上拉电阻。由于通过选择位线上拉电阻来调整感测跳变点，一对上拉电阻和下拉电阻一起调节，以调整参考电压发生器的阻抗。包括比特单元的并联连接的泄漏路径模拟结构被添加到参考电压发生器。泄漏路径模拟结构模仿电子熔丝阵列中的位线上的位单元。位线上的漏电流将位线电压抵消一定的误差电压。在存在泄漏的情况下，参考电压也被误差电压的一部分偏移以平衡'1'和'0'余量水平的偏移。

16. 发明授权

US07687883B2 Electronically programmable antifuse and circuits made therewith 有权
标题翻译：电子可编程反熔丝和由其制成的电路
公开(公告)号：US07687883B2
公开(公告)日：2010-03-30
申请号：US11627723
申请日：2007-01-26
申请人： John A. Fifield , Wagdi W. Abadeer , William R. Tonti
发明人： John A. Fifield , Wagdi W. Abadeer , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).
摘要翻译：一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

17. 发明申请

US20100001788A1 SYSTEM TO EVALUATE CHARGE PUMP OUTPUTS AND ASSOCIATED METHODS 审中-公开
标题翻译：评估充电泵输出和相关方法的系统
公开(公告)号：US20100001788A1
公开(公告)日：2010-01-07
申请号：US12168136
申请日：2008-07-06
申请人： John E. Barth, JR. , John A. Fifield , Fadi H. Gebara , Jente B. Kuang , Michael Sperling
发明人： John E. Barth, JR. , John A. Fifield , Fadi H. Gebara , Jente B. Kuang , Michael Sperling
IPC分类号： G05F3/02 , G05F1/10
CPC分类号： H02M3/07
摘要： A system to evaluate charge pump output may include a comparator to compare a charge pump output voltage to a reference voltage to generate a comparison result. The system may also include a divider to divide down a clock signal. The system may further include a logical conjunction unit to operate on the comparison result and the divided down clock signal.
摘要翻译：用于评估电荷泵输出的系统可以包括比较器，用于将电荷泵输出电压与参考电压进行比较以产生比较结果。该系统还可以包括用于分频时钟信号的分频器。该系统还可以包括对比较结果和划分的下降时钟信号进行操作的逻辑连接单元。

18. 发明授权

US07573300B2 Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same 有权
标题翻译：集成电路中动态逻辑门控电路的电流控制机制及其调节方法
公开(公告)号：US07573300B2
公开(公告)日：2009-08-11
申请号：US11623112
申请日：2007-01-15
申请人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
摘要翻译：一种集成电路，其包括栅极控制电压发生器，其将电流控制栅极电压提供给各自具有保持电路的相应多个动态逻辑电路的多个电流控制装置。栅极控制电压发生器通过电流控制栅极电压提供流过保持器电路的保持器电流量的全局控制，以便增强动态逻辑电路的性能。

19. 发明申请

US20090179670A1 PERFORMANCE INVERSION DETECTION CIRCUIT AND A DESIGN STRUCTURE FOR THE SAME 审中-公开
标题翻译：性能反相检测电路及其设计结构
公开(公告)号：US20090179670A1
公开(公告)日：2009-07-16
申请号：US12014430
申请日：2008-01-15
申请人： Albert M. Chu , John A. Fifield , Daryl M. Seitzer , Hongfei Wu
发明人： Albert M. Chu , John A. Fifield , Daryl M. Seitzer , Hongfei Wu
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F2200/447 , H03F2203/45586 , H03F2203/45618 , H03F2203/45622
摘要： A circuit containing a parallel connection of a first sub-circuit and a second sub-circuit is provided. The first sub-circuit comprises a serial connection of a first field effect transistor having a first threshold voltage and a first voltage dividing device. The second sub-circuit comprises a serial connection of a second field effect transistor having a second threshold voltage, which is different from the first threshold voltage, and a second voltage dividing device. The voltage between the first field effect transistor and the first voltage dividing device is compared with the voltage between the second field effect transistor and the second voltage dividing device so that a signal may be generated at a temperature at which the ratio of a performance parameter such as on-current between the first and second field effect transistors crosses over a predefined value. The signal may be advantageously employed to actively control circuit characteristics.
摘要翻译：提供了包含第一子电路和第二子电路的并联连接的电路。第一子电路包括具有第一阈值电压的第一场效应晶体管和第一分压装置的串联连接。第二子电路包括具有与第一阈值电压不同的第二阈值电压的第二场效应晶体管的串联连接和第二分压装置。将第一场效应晶体管和第一分压装置之间的电压与第二场效应晶体管和第二分压装置之间的电压进行比较，使得可以在这样的温度下产生信号，因为第一和第二场效应晶体管之间的导通电流跨越预定值。可以有利地使用该信号来主动地控制电路特性。

20. 发明申请

US20090033408A1 Voltage Pump Circuit with an Oxide Stress Control Mechanism for use in High-Voltage Applications in an Integrated Circuit 审中-公开
标题翻译：具有用于集成电路中的高压应用的氧化物应力控制机构的电压泵电路
公开(公告)号：US20090033408A1
公开(公告)日：2009-02-05
申请号：US12242233
申请日：2008-09-30
申请人： John A. Fifield
发明人： John A. Fifield
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , H03K17/063 , H03K17/08142 , H03K17/6872 , H03K2217/0027
摘要： A voltage pump circuit that has an oxide stress control mechanism is disclosed. In particular, the oxide stress control mechanism of the voltage pump circuit ensures a safe transistor gate-to-source voltage in high-voltage applications in an integrated circuit. In particular, the down level of the gate voltage of the output transistor may be conditionally limited. For example, an offset in the down level of the gate voltage is created by conditionally developing an offset voltage in the lower rail voltage of the gate driver. The offset voltage is created by directing a predetermined current through a resistance. The current is conditional such that the current is about zero when the power supply voltage is less than or equal to a predetermined level, and the current is greater than zero when the power supply voltage is greater than a predetermined level.
摘要翻译：公开了具有氧化物应力控制机构的电压泵电路。特别地，电压泵电路的氧化物应力控制机构确保在集成电路中的高压应用中的安全的晶体管栅极 - 源极电压。特别地，可以有条件地限制输出晶体管的栅极电压的下降电平。例如，栅极电压的下降电平的偏移是通过有选择地在栅极驱动器的较低轨道电压中产生偏移电压来产生的。通过引导预定电流通过电阻产生偏移电压。电流是有条件的，使得当电源电压小于或等于预定电平时电流约为零，当电源电压大于预定电平时，电流大于零。

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