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    • 15. 发明申请
    • Design Method and System for Minimizing Blind Via Current Loops
    • 设计方法和系统,最大限度地减少盲电流环路
    • US20090031270A1
    • 2009-01-29
    • US11829179
    • 2007-07-27
    • Daniel DourietAnand HaridassAndreas HuberRoger D. Weekly
    • Daniel DourietAnand HaridassAndreas HuberRoger D. Weekly
    • G06F17/50
    • G06F17/5081H05K1/0216H05K1/115H05K3/0005H05K2201/09636
    • A design method and system for minimizing blind via current loops provides for improvement of electrical interconnect structure design without requiring extensive electromagnetic analysis. Other vias in the vicinity of a blind via carrying a critical signal are checked for suitability to conduct return current corresponding to the critical signal that is disrupted by the transition from a layer between two metal planes to another layer. The distance to the return current via(s) is checked and the design is adjusted to reduce the distance if the distance is greater than a specified threshold. If the blind via transition is to an external layer, suitable vias connect the reference plane at the internal end of the blind via to an external terminal. If the transition is between internal layers, suitable vias are vias that connect the two reference planes surrounding the reference plane traversed by the blind via.
    • 用于最小化盲通过电流回路的设计方法和系统提供了电互连结构设计的改进,而不需要广泛的电磁分析。 检查通过携带关键信号的盲目附近的其他通孔是否​​适合于进行对应于由两个金属平面之间的层到另一层之间的过渡而被破坏的关键信号的返回电流。 检查通过(s)的返回电流的距离,并且如果距离大于指定的阈值,则设计被调整以减小距离。 如果盲目通过转换到外部层,合适的通孔将盲通孔内部的参考平面连接到外部端子。 如果过渡在内层之间,合适的通孔是连接围绕由盲孔通过的参考平面的两个参考平面的通孔。