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11. 发明申请

US20120300550A1 Ramping Pass Voltage To Enhance Channel Boost In Memory Device, With Optional Temperature Compensation 有权
标题翻译：缓存通过电压，以增强存储器件中的通道升压，具有可选的温度补偿
公开(公告)号：US20120300550A1
公开(公告)日：2012-11-29
申请号：US13113786
申请日：2011-05-23
申请人： Gerrit Jan Hemink , Shih-Chung Lee , Anubhav Khandelwal , Henry Chin , Guirong Liang , Dana Lee
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Anubhav Khandelwal , Henry Chin , Guirong Liang , Dana Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C16/10
摘要： In a non-volatile storage system, one or more substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. A voltage applied to one or more unselected word lines associated with at least a first channel region is increased during a program pulse time period in which a program pulse is applied to a selected word line. The increase can be gradual, in the form of a ramp, or step-wise. The boosting level of the first channel region can be maintained. The increase in the voltage applied to the one or more unselected word lines can vary with temperature as well. Before the program pulse time period, the voltage applied to the one or more unselected word lines can be ramped up at a faster rate for a second, adjacent channel region than for the first channel region, to help isolate the channel regions.
摘要翻译：在非易失性存储系统中，用于未选择的NAND串的一个或多个衬底沟道区在编程期间升高以抑制编程干扰。在将编程脉冲施加到所选字线的编程脉冲时间段期间，施加到与至少第一信道区域相关联的一个或多个未选择字线的电压增加。增加可以是渐进的，以斜坡的形式，或逐步的。可以维持第一通道区域的升压水平。施加到一个或多个未选择字线的电压的增加也随着温度而变化。在编程脉冲时间段之前，施加到一个或多个未选择字线的电压可以以比第一通道区域更快的速率向第二相邻通道区域上升，以帮助隔离通道区域。

12. 发明授权

US08164135B2 Non-diffusion junction split-gate nonvolatile memory cells and arrays, methods of programming, erasing, and reading thereof, and methods of manufacture 有权
标题翻译：非扩散结分离栅极非易失性存储器单元和阵列，其编程，擦除和读取方法以及制造方法
公开(公告)号：US08164135B2
公开(公告)日：2012-04-24
申请号：US12773811
申请日：2010-05-04
申请人： Changyuan Chen , Ya-Fen Lin , Dana Lee
发明人： Changyuan Chen , Ya-Fen Lin , Dana Lee
IPC分类号： H01L29/788
CPC分类号： G11C16/0458 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42336 , H01L29/7887
摘要： Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.
摘要翻译：公开了非挥发性闪速存储器系统和方法，其具有第一导电类型的半导体衬底，包括非扩散沟道区，通过向相关联的栅极元件施加电压而引起电子流。多个浮动栅极彼此间隔开并且与沟道区域绝缘。多个控制栅极彼此间隔开并且与沟道区域绝缘，每个控制栅极位于第一浮动栅极和第二浮动栅极之间，并电容耦合到其上以形成子电池。多个间隔开的辅助栅极与沟道区域绝缘，每个辅助栅极位于相邻子电池之间并且与相邻的子电池绝缘。通道由三个区域组成，两个位于相邻的控制栅极元件下方，以及位于相关联的辅助栅极之间的第一个两个和第二区域之间。

13. 发明授权

US07800956B2 Programming algorithm to reduce disturb with minimal extra time penalty 有权
标题翻译：编程算法以最小的额外时间损失来减少干扰
公开(公告)号：US07800956B2
公开(公告)日：2010-09-21
申请号：US12163073
申请日：2008-06-27
申请人： Dana Lee , Deepanshu Dutta , Yingda Dong
发明人： Dana Lee , Deepanshu Dutta , Yingda Dong
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all high state cells are programmed in the first programming pass.
摘要翻译：在多遍编程过程中，非易失性存储器中的编程时间会减少。在第一编程通道中，高状态单元通过一系列编程脉冲进行编程，以识别快速和慢速的高状态单元，而较低状态单元被从编程中锁定。一旦识别，快速高状态单元暂时被禁止编程，而缓慢的高状态单元继续被编程到其最终预期状态。此外，编程脉冲急剧地升高以对慢速高状态单元进行编程。在第二个编程过程中，快速高状态单元与其他较低状态单元一起编程，直到它们都达到各自的预期状态。与在第一编程通路中编程所有高状态单元的方法相比，实现了时间节省。

14. 发明授权

US07577034B2 Reducing programming voltage differential nonlinearity in non-volatile storage 有权
标题翻译：降低非易失性存储器中的编程电压差分非线性
公开(公告)号：US07577034B2
公开(公告)日：2009-08-18
申请号：US11861909
申请日：2007-09-26
申请人： Dana Lee , Jun Wan
发明人： Dana Lee , Jun Wan
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C29/00
摘要： A corrective action is taken to adjust for nonlinearities in a program voltage which is applied to a selected word line in a memory device. The nonlinearities result in a non-uniform program voltage step size which can cause over programming or slow programming. A digital to analog converter (DAC) which provides the program voltages can have a nonlinear output, such as when certain code words are input to the DAC. The memory device can be tested beforehand to determine where the nonlinearities occur, and configured to take corrective action when the corresponding code words are input. For example, the DAC may have a nonlinear output when a rollover code word is input, e.g., a when a string of least significant bits in successive code words change from 1's to 0's. The corrective action can include repeating a prior program pulse or adjusting a duration of a program pulse.
摘要翻译：采取校正动作来调整应用于存储器件中的选定字线的编程电压中的非线性。非线性导致不均匀的程序电压步长，这可能导致过度编程或缓慢编程。提供程序电压的数模转换器（DAC）可以具有非线性输出，例如当某些代码字被输入到DAC时。可以预先测试存储器件以确定非线性发生的位置，并且配置为在输入相应的代码字时采取校正动作。例如，当输入翻转代码字时，DAC可以具有非线性输出，例如，当连续代码字中的最低有效位的串从1变为0时。校正动作可以包括重复先前的编程脉冲或调整编程脉冲的持续时间。

15. 发明申请

US20090161433A1 Regulation of Source Potential to Combat Cell Source IR Drop 有权
标题翻译：源细胞源IR滴的源电位调节
公开(公告)号：US20090161433A1
公开(公告)日：2009-06-25
申请号：US11961871
申请日：2007-12-20
申请人： Dana Lee , Nima Mokhlesi , Deepak Chandra Sekar
发明人： Dana Lee , Nima Mokhlesi , Deepak Chandra Sekar
IPC分类号： G11C16/10 , G11C16/26
CPC分类号： G11C16/30
摘要： Techniques are presented for dealing with possible source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits of a non-volatile memory. The error is caused by a voltage drop across the resistance of the source path to the chip's ground when current flows. For this purpose, the memory device includes a source potential regulation circuit, including an active circuit element having a first input connected to a reference voltage and having a second input connected as a feedback loop that is connectable to the aggregate node from which the memory cells of a structural block have their current run to ground. A variation includes a non-linear resistive element connectable between the aggregate node and ground.
摘要翻译：提出用于处理可能的源极偏置的技术是由非易失性存储器的读/写电路的接地回路中的非零电阻引入的误差。误差是由电流流动时芯片地线源极电阻的电压降引起的。为此，存储器件包括源极电位调节电路，其包括有源电路元件，该有源电路元件具有连接到参考电压的第一输入端，并且具有连接到反馈回路的第二输入端，该反馈回路可连接到汇集节点，存储器单元的结构块现在已经跑到地面上了。变化包括可在聚集节点和地之间连接的非线性电阻元件。

16. 发明授权

US07544569B2 Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing 有权
标题翻译：双向分闸门NAND闪存结构和阵列，编程方法，擦除和读取方法以及制造方法
公开(公告)号：US07544569B2
公开(公告)日：2009-06-09
申请号：US11516431
申请日：2006-09-05
申请人： Feng Gao , Ya-Fen Lin , John W. Cooksey , Changyuan Chen , Yuniarto Widjaja , Dana Lee
发明人： Feng Gao , Ya-Fen Lin , John W. Cooksey , Changyuan Chen , Yuniarto Widjaja , Dana Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/42336 , G11C16/0425 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11556 , H01L29/42328
摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.
摘要翻译：在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括第二导电类型的第一区域和第二导电类型的第二区域，与第一区域间隔开，由此在其间限定沟道区域。多个浮动栅极彼此间隔开并且各自与沟道区域绝缘。多个控制栅极彼此间隔开，每个控制栅极与沟道区域绝缘。每个控制栅极位于一对浮动栅极之间，并且电容耦合到该对浮置栅极。多个选择栅极彼此间隔开，每个选择栅极与沟道区域绝缘。每个选择门位于一对浮动门之间。

17. 发明申请

US20090016113A1 NON-DIFFUSION JUNCTION SPLIT-GATE NONVOLATILE MEMORY CELLS AND ARRAYS, METHODS OF PROGRAMMING, ERASING, AND READING THEREOF, AND METHODS OF MANUFACTURE 有权
标题翻译：非扩散结分离门非易失性记忆细胞和阵列，其编程，消除和阅读方法及其制造方法
公开(公告)号：US20090016113A1
公开(公告)日：2009-01-15
申请号：US11775851
申请日：2007-07-10
申请人： Changyuan Chen , Ya-Fen Lin , Dana Lee
发明人： Changyuan Chen , Ya-Fen Lin , Dana Lee
IPC分类号： G11C16/06 , H01L29/788 , G11C16/16
CPC分类号： G11C16/0458 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42336 , H01L29/7887
摘要： Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.
摘要翻译：公开了非挥发性闪速存储器系统和方法，其具有第一导电类型的半导体衬底，包括非扩散沟道区，通过向相关联的栅极元件施加电压而引起电子流。多个浮动栅极彼此间隔开并且与沟道区域绝缘。多个控制栅极彼此间隔开并且与沟道区域绝缘，每个控制栅极位于第一浮动栅极和第二浮动栅极之间，并电容耦合到其上以形成子电池。多个间隔开的辅助栅极与沟道区域绝缘，每个辅助栅极位于相邻子电池之间并且与相邻的子电池绝缘。通道由三个区域组成，两个位于相邻的控制栅极元件下方，以及位于相关联的辅助栅极之间的第一个两个和第二区域之间。

18. 发明授权

US07439572B2 Stacked gate memory cell with erase to gate, array, and method of manufacturing 有权
标题翻译：具有擦除到栅极，阵列和制造方法的堆叠栅极存储单元
公开(公告)号：US07439572B2
公开(公告)日：2008-10-21
申请号：US11303567
申请日：2005-12-15
申请人： Bomy Chen , Hieu Van Tran , Dana Lee , Jack Edward Frayer
发明人： Bomy Chen , Hieu Van Tran , Dana Lee , Jack Edward Frayer
IPC分类号： H01L29/788 , H01L29/76
CPC分类号： H01L27/11521 , G11C16/0491 , H01L27/115 , H01L29/7885
摘要： A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injecton from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.
摘要翻译：堆叠式非易失性存储器浮栅器件具有控制栅极。通过从漏极到浮动栅极的热通道电子注入来实现阵列中的单元的编程。擦除由Fowler-Nordheim发生，电子从浮动栅极隧道到控制门。最后，为了增加密度，可以在沟槽中制造每个单元。

19. 发明授权

US07399678B2 Method for reading an array of multi-bit ROM cells with each cell having bi-directional read 有权
标题翻译：用于读取具有双向读取的每个单元的多位ROM单元阵列的方法
公开(公告)号：US07399678B2
公开(公告)日：2008-07-15
申请号：US11292557
申请日：2005-12-02
申请人： Dana Lee , Bomy Chen
发明人： Dana Lee , Bomy Chen
IPC分类号： H01L21/8234
CPC分类号： H01L27/11266 , G11C11/5692 , G11C17/12 , H01L27/112
摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.
摘要翻译：多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。通道在第一和第二区域之间。通道具有三个部分，第一部分，第二部分和第三部分。门间隔开并与通道的至少第二部分绝缘。每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻第一区域和/或与第二区域相邻的通道的第三部分。在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

20. 发明申请

US20080151628A1 SYSTEM FOR LOW VOLTAGE PROGRAMMING OF NON-VOLATILE MEMORY CELLS 有权
标题翻译：非挥发性记忆体低电压编程系统
公开(公告)号：US20080151628A1
公开(公告)日：2008-06-26
申请号：US11614884
申请日：2006-12-21
申请人： Dana Lee , Jeffrey Lutze
发明人： Dana Lee , Jeffrey Lutze
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C16/10
摘要： System for programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n).
摘要翻译：用于通过从注入存储器单元的漏极区域注入热载流子来对存储器阵列中的所选择的非易失性存储单元进行编程的系统，所述存储器阵列具有耦合到字线WL（n）的栅极节点和连接到所选位线的漏极节点门节点与下一个相邻字线WL（n-1）耦合到字线WL（n）上的所选择的非易失性存储器单元的浮动栅极。

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