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11. 发明授权

US07777293B2 Semiconductor integrated circuit, D-A converter device, and A-D converter device 有权
标题翻译：半导体集成电路，D-A转换器和A-D转换器
公开(公告)号：US07777293B2
公开(公告)日：2010-08-17
申请号：US10898965
申请日：2004-07-27
申请人： Yoshinori Miyada , Kenji Murata , Daisuke Nomasaki
发明人： Yoshinori Miyada , Kenji Murata , Daisuke Nomasaki
IPC分类号： H01L29/93
CPC分类号： H01L27/0805 , H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.
摘要翻译：半导体集成电路具有多个电容器单元，并且每个电容器单元具有上电极和下电极。这些电极分别连接到上电极布线和下电极。当例如上电极连接到上电极布线并且电极布线位于另一个电容器单元的下电极的一侧或连接这些电极的下电极布线的一侧时，屏蔽布线设置在上电极布线和另一个电容器单元的相邻位置的下电极或上电极布线和相邻位置的下电极布线之间。因此，利用该屏蔽布线，可以有效地抑制电容器单元的各布线与电容器单元的每个上电极或每个下电极之间的电容耦合。

12. 发明授权

US06927723B2 A/D converter and A/D conversion method 失效
标题翻译： A / D转换器和A / D转换方法
公开(公告)号：US06927723B2
公开(公告)日：2005-08-09
申请号：US10855397
申请日：2004-05-28
申请人： Daisuke Nomasaki , Kenji Murata , Hideki Tanaka , Yoshinori Miyada
发明人： Daisuke Nomasaki , Kenji Murata , Hideki Tanaka , Yoshinori Miyada
IPC分类号： H03M1/12 , H03M1/46
CPC分类号： H03M1/124 , H03M1/468
摘要： In a charge redistribution type A/D converter, an input-side capacitor terminal and a comparator-side capacitor terminal are connected through first and second analog switches to a fixed-voltage supply circuit, and the input-side capacitor terminal is connected through a third analog switch to the outside. Immediately before sampling an analog signal, the first and second analog switches are closed while the third analog switch is opened, according to a RESET signal. Thereby, fixed voltages are supplied to the input-side capacitor terminal and the comparator-side capacitor terminal, respectively, and charge stored in a weighting capacitor unit is initialized to a predetermined value.
摘要翻译：在电荷再分配型A / D转换器中，输入侧电容器端子和比较器侧电容器端子通过第一和第二模拟开关连接到固定电压电源电路，并且输入侧电容器端子通过第三个模拟开关到外面。在采样模拟信号之前，根据RESET信号，第三模拟开关打开时，第一和第二模拟开关闭合。由此，固定电压分别被提供给输入侧电容器端子和比较器侧电容器端子，并将存储在加权电容器单元中的电荷初始化为预定值。

13. 发明申请

US20050001291A1 Semiconductor integrated circuit, D-A converter device, and A-D converter device 有权
标题翻译：半导体集成电路，D-A转换器和A-D转换器
公开(公告)号：US20050001291A1
公开(公告)日：2005-01-06
申请号：US10898965
申请日：2004-07-27
申请人： Yoshinori Miyada , Kenji Murata , Daisuke Nomasaki
发明人： Yoshinori Miyada , Kenji Murata , Daisuke Nomasaki
IPC分类号： H01L27/04 , H01L21/822 , H01L23/522 , H01L27/08 , H01L23/552
CPC分类号： H01L27/0805 , H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.
摘要翻译：半导体集成电路具有多个电容器单元，并且每个电容器单元具有上电极和下电极。这些电极分别连接到上电极布线和下电极。当例如上电极连接到上电极布线并且电极布线位于另一个电容器单元的下电极的一侧或连接这些电极的下电极布线的一侧时，屏蔽布线设置在上电极布线和另一个电容器单元的相邻位置的下电极或上电极布线和相邻位置的下电极布线之间。因此，利用该屏蔽布线，可以有效地抑制电容器单元的各布线与电容器单元的每个上电极或每个下电极之间的电容耦合。

14. 发明授权

US06777775B2 Semiconductor integrated circuit, D-A converter device, and A-D converter device 有权
标题翻译：半导体集成电路，D-A转换器和A-D转换器
公开(公告)号：US06777775B2
公开(公告)日：2004-08-17
申请号：US10187378
申请日：2002-07-02
申请人： Yoshinori Miyada , Kenji Murata , Daisuke Nomasaki
发明人： Yoshinori Miyada , Kenji Murata , Daisuke Nomasaki
IPC分类号： H01L2900
CPC分类号： H01L27/0805 , H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.
摘要翻译：半导体集成电路具有多个电容器单元，并且每个电容器单元具有上电极和下电极。这些电极分别连接到上电极布线和下电极。当例如上电极连接到上电极布线并且电极布线位于另一个电容器单元的下电极的一侧或连接这些电极的下电极布线的一侧时，屏蔽布线设置在上电极布线和另一个电容器单元的相邻位置的下电极或上电极布线和相邻位置的下电极布线之间。因此，利用该屏蔽布线，可以有效地抑制电容器单元的各布线与电容器单元的每个上电极或每个下电极之间的电容耦合。

15. 发明授权

US06741192B2 A/D conversion method for serial/parallel A/D converter, and serial/parallel A/D converter 失效
标题翻译：串行/并行A / D转换器和串行/并行A / D转换器的A / D转换方法
公开(公告)号：US06741192B2
公开(公告)日：2004-05-25
申请号：US10615391
申请日：2003-07-09
申请人： Kenji Murata , Daisuke Nomasaki
发明人： Kenji Murata , Daisuke Nomasaki
IPC分类号： H03M900
CPC分类号： H03M1/148 , H03M1/362
摘要： The present invention provides a serial/parallel A/D converter which is capable of performing a high-speed and high-accuracy operation even in the case where an analog input voltage Vin greatly varies in a period between a previous sampling period in which the analog input voltage is held and the next sampling period, when converting the analog input voltage Vin input into a digital value. This serial/parallel A/D converter includes a lower-order reference voltage initializing circuit 8 for initializing a lower-order reference voltage to an initialization voltage Vrc 23. The initialization voltage Vrc 23 is generated as the lower-order reference voltage in an arbitrary period from the start of sampling of the analog input voltage until the start of a comparison operation for the lower-order reference voltage, the value of the lower-order reference voltage is changed from the value of the initialization voltage to a voltage value which is decided on the basis of higher-order code selection signals P0C-P3C from a higher-order code selecting circuit 14, and the value of the lower-order reference voltage which is decided on the basis of the higher-order code selection signals P0C-P3C is compared with the value of the analog input voltage.
摘要翻译：本发明提供一种串行/并行A / D转换器，其即使在模拟输入电压Vin在先前的采样周期之间的时段内大大变化的情况下也能够执行高速和高精度的操作，其中模拟当将模拟输入电压Vin输入转换为数字值时，保持输入电压和下一个采样周期。该串/并行A / D转换器包括用于将低阶参考电压初始化为初始化电压Vrc 23的低阶参考电压初始化电路8.初始化电压Vrc 23作为任意的低阶参考电压生成从开始对模拟输入电压的采样开始到低阶参考电压的比较操作开始之间的时间段，将低阶参考电压的值从初始化电压的值改变为电压值，即，基于来自高阶代码选择电路14的高阶代码选择信号P0C-P3C和基于较高阶代码选择信号P0C-P3C决定的低阶参考电压的值， P3C与模拟输入电压的值进行比较。

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