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11. 发明授权

US07445976B2 Method of forming a semiconductor device having an interlayer and structure therefor 有权
标题翻译：形成具有中间层的半导体器件及其结构的方法
公开(公告)号：US07445976B2
公开(公告)日：2008-11-04
申请号：US11420525
申请日：2006-05-26
申请人： James K. Schaeffer , Rama I. Hegde , Srikanth B. Samavedam
发明人： James K. Schaeffer , Rama I. Hegde , Srikanth B. Samavedam
IPC分类号： H01L21/00
CPC分类号： H01L21/823857 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L29/4966 , H01L29/517
摘要： A stack located over a substrate. The stack includes a layer between a dielectric layer and a metal layer. The layer includes a halogen and a metal. In one embodiment, the halogen is fluorine. In one embodiment, the stack is a control electrode stack for a transistor. In one example the control electrode stack is a gate stack for a MOSFET. In one example, the layer includes aluminum fluoride.
摘要翻译：位于衬底上方的堆叠。堆叠包括介电层和金属层之间的层。该层包括卤素和金属。在一个实施方案中，卤素是氟。在一个实施例中，堆叠是用于晶体管的控制电极堆叠。在一个示例中，控制电极堆叠是用于MOSFET的栅极堆叠。在一个实例中，该层包括氟化铝。

12. 发明授权

US06320784B1 Memory cell and method for programming thereof 有权
标题翻译：存储单元及其编程方法
公开(公告)号：US06320784B1
公开(公告)日：2001-11-20
申请号：US09524916
申请日：2000-03-14
申请人： Ramachandran Muralidhar , Sucharita Madhukar , Bo Jiang , Bruce E. White , Srikanth B. Samavedam , David L. O'Meara , Michael Alan Sadd
发明人： Ramachandran Muralidhar , Sucharita Madhukar , Bo Jiang , Bruce E. White , Srikanth B. Samavedam , David L. O'Meara , Michael Alan Sadd
IPC分类号： G11C1100
CPC分类号： B82Y10/00 , G11C11/56 , G11C11/5671 , G11C16/0416 , G11C2216/08 , H01L29/7887 , H01L29/7888
摘要： A memory cell (101), its method of formation, and operation are disclosed. In accordance with one embodiment, the memory cell (101) comprises a first and second current carrying electrode (12) a control electrode (19), and doped discontinuous storage elements (17). In accordance with an alternative embodiment, memory cell programming is accomplished by removing or adding an average of approximately at least a first charge (30, 62, 64), which can be electron(s) or hole(s) from each of the doped discontinuous storage elements (17).
摘要翻译：公开了一种存储单元（101），其形成方法和操作。根据一个实施例，存储单元（101）包括第一和第二载流电极（12），控制电极（19）和掺杂的非连续存储元件（17）。根据替代实施例，存储器单元编程通过去除或添加大约至少第一电荷（30,62,64）的平均值来实现，所述第一电荷可以是来自掺杂的每一个的电子或空穴不连续存储元件（17）。

13. 发明授权

US09362280B2 Semiconductor devices with different dielectric thicknesses 有权
公开(公告)号：US09362280B2
公开(公告)日：2016-06-07
申请号：US13893026
申请日：2013-05-13
申请人： Gauri V. Karve , Mark D. Hall , Srikanth B. Samavedam
发明人： Gauri V. Karve , Mark D. Hall , Srikanth B. Samavedam
IPC分类号： H01L21/70 , H01L27/092 , H01L21/8238 , H01L29/10
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823857 , H01L29/1054
摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.

14. 发明授权

US08460996B2 Semiconductor devices with different dielectric thicknesses 有权
标题翻译：具有不同介电厚度的半导体器件
公开(公告)号：US08460996B2
公开(公告)日：2013-06-11
申请号：US11931565
申请日：2007-10-31
申请人： Gauri V. Karve , Mark D. Hall , Srikanth B. Samavedam
发明人： Gauri V. Karve , Mark D. Hall , Srikanth B. Samavedam
IPC分类号： H01L21/8242
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823857 , H01L29/1054
摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.
摘要翻译：具有具有不同厚度的电介质层的器件的集成电路。电介质层包括高k电介质，并且一些电介质层包括由氧化工艺形成的氧化物层。每个器件包括位于器件的电极堆叠下方的包含锗或碳的层。硅层位于包含锗或碳的层之上。

15. 发明申请

US20080001202A1 A METHOD OF MAKING METAL GATE TRANSISTORS 失效
标题翻译：制造金属栅极晶体管的方法
公开(公告)号：US20080001202A1
公开(公告)日：2008-01-03
申请号：US11427980
申请日：2006-06-30
申请人： James K. Schaeffer , David C. Gilmer , Mark V. Raymond , Philip J. Tobin , Srikanth B. Samavedam
发明人： James K. Schaeffer , David C. Gilmer , Mark V. Raymond , Philip J. Tobin , Srikanth B. Samavedam
IPC分类号： H01L29/94
CPC分类号： H01L27/1203 , H01L21/28105 , H01L21/823842 , H01L21/84 , H01L29/4966 , H01L29/517
摘要： A semiconductor device has a gate with three conductive layers over a high K gate dielectric. The first layer is substantially oxygen free. The work function is modulated to the desired work function by a second conductive layer in response to subsequent thermal processing. The second layer is a conductive oxygen-bearing metal. With sufficient thickness of the first layer, there is minimal penetration of oxygen from the second layer through the first layer to adversely impact the gate dielectric but sufficient penetration of oxygen to change the work function to a more desirable level. A third layer, which is metallic, is deposited over the second layer. A polysilicon layer is deposited over the third layer. The third layer prevents the polysilicon layer and the oxygen-bearing layer from reacting together.
摘要翻译：半导体器件具有在高K栅极电介质上的具有三个导电层的栅极。第一层基本上是无氧的。响应于随后的热处理，功函数被第二导电层调制到期望的功函数。第二层是导电含氧金属。具有足够的第一层的厚度，氧从第二层穿过第一层的最小穿透而不利地影响栅极电介质，但充分渗入氧气以将功函数改变到更理想的水平。金属的第三层沉积在第二层上。多晶硅层沉积在第三层上。第三层防止多晶硅层和含氧层一起反应。

16. 发明授权

US06894353B2 Capped dual metal gate transistors for CMOS process and method for making the same 有权
标题翻译：用于CMOS工艺的双金属栅极晶体管及其制造方法
公开(公告)号：US06894353B2
公开(公告)日：2005-05-17
申请号：US10209523
申请日：2002-07-31
申请人： Srikanth B. Samavedam , Philip J. Tobin
发明人： Srikanth B. Samavedam , Philip J. Tobin
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L21/823835 , H01L21/823814 , H01L21/823842 , H01L21/823864
摘要： A first gate (120) and a second gate (122) are preferably PMOS and NMOS transistors, respectively, formed in an n-type well (104) and a p-type well (106). In a preferred embodiment first gate (120) includes a first metal layer (110) of titanium nitride on a gate dielectric (108), a second metal layer (114) of tantalum silicon nitride and a silicon containing layer (116) of polysilicon. Second gate (122) includes second metal layer (114) of a tantalum silicon nitride layer on the gate dielectric (108) and a silicon containing layer (116) of polysilicon. First spacers (124) are formed adjacent the sidewalls of the gates to protect the metals from chemistries used to remove photoresist masks during implant steps. Since the chemistries used are selective to polysilicon, the spacers (124) need not protect the polysilicon capping layers, thereby increasing the process margin of the spacer etch process. The polysilicon cap also facilitates silicidation of the gates.
摘要翻译：第一栅极（120）和第二栅极（122）分别优选分别形成在n型阱（104）和p型阱（106）中的PMOS和NMOS晶体管。在优选实施例中，第一栅极（120）包括在栅极电介质（108）上的氮化钛的第一金属层（110），氮化硅钽的第二金属层（114）和多晶硅的含硅层（116）。第二栅极（122）包括栅极电介质（108）上的氮化硅钽层的第二金属层（114）和多晶硅的含硅层（116）。邻近门的侧壁形成第一间隔物（124），以在植入步骤期间保护用于去除光致抗蚀剂掩模的化学物质的金属。由于使用的化学物质对多晶硅是选择性的，间隔物（124）不需要保护多晶硅覆盖层，从而增加间隔物蚀刻工艺的工艺边缘。多晶硅帽也有利于栅极的硅化。

17. 发明授权

US06475841B1 Transistor with shaped gate electrode and method therefor 失效
标题翻译：具有形状栅电极的晶体管及其方法
公开(公告)号：US06475841B1
公开(公告)日：2002-11-05
申请号：US09584963
申请日：2000-06-02
申请人： William J. Taylor, Jr. , Srikanth B. Samavedam , Nigel Cave
发明人： William J. Taylor, Jr. , Srikanth B. Samavedam , Nigel Cave
IPC分类号： H01L21311
CPC分类号： H01L29/4916 , H01L21/26586 , H01L21/28114 , H01L21/823437 , H01L21/823456 , H01L21/823828 , H01L21/823842 , H01L21/82385 , H01L29/42376
摘要： A transistor structure includes a retrograde gate structure (112) that is narrower at the end that interfaces with the gate dielectric (120) than it is at the opposite end and method for manufacture of such a structure. The retrograde gate structure (112) is formed by depositing a layer of gate material (104) that has varying composition in the vertical direction. The differentiation in composition causes varying lateral etch rate characteristics along the vertical direction of the gate structure (112) such that increased etching of the gate material (104) occurs near the interface with the gate dielectric layer (102).
摘要翻译：晶体管结构包括在与栅极电介质（120）接合的端部处比在相反端更窄的逆向栅极结构（112）和用于制造这种结构的方法。逆行栅极结构（112）通过在垂直方向上沉积具有不同组成的栅极材料层（104）而形成。组成的区别导致沿着栅极结构（112）的垂直方向的不同的横向蚀刻速率特性，使得栅极材料（104）的增加的蚀刻发生在与栅极介电层（102）的界面附近。

18. 发明授权

US6039803A Utilization of miscut substrates to improve relaxed graded silicon-germanium and germanium layers on silicon 失效
标题翻译：利用捣碎基板来改善硅上松弛的分级硅 - 锗和锗层
公开(公告)号：US6039803A
公开(公告)日：2000-03-21
申请号：US806741
申请日：1997-02-27
申请人： Eugene A. Fitzgerald , Srikanth B. Samavedam
发明人： Eugene A. Fitzgerald , Srikanth B. Samavedam
IPC分类号： C30B25/18 , H01L21/20
CPC分类号： C30B25/18 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/0251 , H01L21/02521 , H01L21/02532 , Y10S117/902
摘要： A method of processing semiconductor materials, including providing a monocrystalline silicon substrate having a (001) crystallographic surface orientation; off-cutting the substrate to an orientation from about 2.degree. to about 6.degree. offset towards the [110] direction; and epitaxially growing a relaxed graded layer of a crystalline GeSi on the substrate. A semiconductor structure including a monocrystalline silicon substrate having a (001) crystallographic surface orientation, the substrate being off-cut to an orientation from about 2.degree. to about 6.degree. offset towards the [110] direction; and a relaxed graded layer of a crystalline GeSi which is epitaxially grown on the substrate.
摘要翻译：一种处理半导体材料的方法，包括提供具有（001）晶面取向的单晶硅衬底; 将基板切割成朝向[110]方向偏移约2°至约6°的取向; 并且在衬底上外延生长结晶GeSi的缓和梯度层。一种半导体结构，其包括具有（001）结晶表面取向的单晶硅衬底，所述衬底偏离朝向[110]方向偏移约2度至约6度的取向; 以及在衬底上外延生长的结晶GeSi的弛豫梯度层。

19. 发明授权

US08003454B2 CMOS process with optimized PMOS and NMOS transistor devices 有权
标题翻译： CMOS工艺具有优化的PMOS和NMOS晶体管器件
公开(公告)号：US08003454B2
公开(公告)日：2011-08-23
申请号：US12125855
申请日：2008-05-22
申请人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
发明人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
IPC分类号： H01L21/336 , H01L21/337
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L29/1054 , H01L29/6659 , H01L29/66636 , H01L29/66651 , H01L29/7843 , H01L29/7848
摘要： A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.
摘要翻译：半导体工艺和装置包括通过选择性地缓解PMOS器件区域（97）中的双轴拉伸应变半导体层（90）的一部分，在晶体管的沟道区域中形成具有增强的空穴迁移率的NMOS和PMOS晶体管（24,34）以形成松弛半导体层（91），然后在形成覆盖沟道区域的NMOS和PMOS栅极结构（26,36）之前外延生长双轴向应力硅锗沟道区域层（22），然后沉积接触蚀刻停止层（53-56）在NMOS和PMOS栅极结构之上。也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。

20. 发明授权

US07683439B2 Semiconductor device having a metal carbide gate with an electropositive element and a method of making the same 有权
标题翻译：具有具有正电性单元的金属碳化物栅极的半导体器件及其制造方法
公开(公告)号：US07683439B2
公开(公告)日：2010-03-23
申请号：US11685027
申请日：2007-03-12
申请人： Srikanth B. Samavedam , David C. Gilmer , Mark V. Raymond , James K. Schaeffer
发明人： Srikanth B. Samavedam , David C. Gilmer , Mark V. Raymond , James K. Schaeffer
IPC分类号： H01L27/088
CPC分类号： H01L29/4966 , H01L21/28088 , H01L29/4908 , H01L29/4958
摘要： A semiconductor device structure is formed over a semiconductor substrate and has a gate dielectric over the semiconductor substrate and a gate over the gate dielectric. The gate, at an interface with the gate dielectric, comprises a transition metal, carbon, and an electropositive element. The transition metal comprises one of group consisting of tantalum, titanium, hafnium, zirconium, molybdenum, and tungsten. The electropositive element comprises one of a group consisting of a Group IIA element, a Group IIIB element, and lanthanide series element.
摘要翻译：半导体器件结构形成在半导体衬底之上并且在半导体衬底上方具有栅极电介质，并且在栅极电介质上方具有栅极。在与栅极电介质的界面处的栅极包含过渡金属，碳和正电性元素。过渡金属由钽，钛，铪，锆，钼和钨组成。正电荷元素包括由IIA族元素，IIIB族元素和镧系元素组成的组中的一种。

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