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11. 发明授权

US06943370B2 Control of memory arrays utilizing zener diode-like devices 有权
标题翻译：使用齐纳二极管状器件来控制存储器阵列
公开(公告)号：US06943370B2
公开(公告)日：2005-09-13
申请号：US10882538
申请日：2004-06-30
申请人： Michael A. VanBuskirk , Colin Bill , Tzu-Ning Fang , Zhida Lan
发明人： Michael A. VanBuskirk , Colin Bill , Tzu-Ning Fang , Zhida Lan
IPC分类号： G11C11/56 , G11C13/02 , G11C16/02 , H01L51/00
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0016 , G11C13/003 , G11C2213/71 , G11C2213/72 , G11C2213/77
摘要： The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.
摘要翻译：本发明通过帮助单个器件改变半导体阵列中的状态的方式来帮助半导体器件。可以将状态变化电压施加到半导体器件阵列中的单个器件，而不需要晶体管型电压控制。本发明的二极体效应通过允许状态改变所需的特定电压水平仅发生在期望的装置来促进该活动。以这种方式，可以在不利用晶体管技术的情况下用不同的数据或状态对器件阵列进行编程。本发明还允许制造这些类型的器件的非常有效的方法，消除了制造昂贵的外部电压控制半导体器件的需要。

12. 发明授权

US06847047B2 Methods that facilitate control of memory arrays utilizing zener diode-like devices 有权
标题翻译：方便使用齐纳二极管状器件来控制存储器阵列
公开(公告)号：US06847047B2
公开(公告)日：2005-01-25
申请号：US10287363
申请日：2002-11-04
申请人： Michael A. VanBuskirk , Colin Bill , Tzu-Ning Fang , Zhida Lan
发明人： Michael A. VanBuskirk , Colin Bill , Tzu-Ning Fang , Zhida Lan
IPC分类号： G11C11/56 , G11C13/02 , G11C16/02 , H01L51/00
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0016 , G11C13/003 , G11C2213/71 , G11C2213/72 , G11C2213/77
摘要： The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.
摘要翻译：本发明通过帮助单个器件改变半导体阵列中的状态的方式来帮助半导体器件。可以将状态变化电压施加到半导体器件阵列中的单个器件，而不需要晶体管型电压控制。本发明的二极体效应通过允许状态改变所需的特定电压水平仅发生在期望的装置来促进该活动。以这种方式，可以在不利用晶体管技术的情况下用不同的数据或状态对器件阵列进行编程。本发明还允许制造这些类型的器件的非常有效的方法，消除了制造昂贵的外部电压控制半导体器件的需要。

13. 发明授权

US6122198A Bit by bit APDE verify for flash memory applications 有权
标题翻译：逐点APDE验证闪存应用程序
公开(公告)号：US6122198A
公开(公告)日：2000-09-19
申请号：US413182
申请日：1999-10-05
申请人： Sameer Shafiq Haddad , Ravi Prakash Gutala , Colin Bill
发明人： Sameer Shafiq Haddad , Ravi Prakash Gutala , Colin Bill
IPC分类号： G11C16/34 , G11C11/34
CPC分类号： G11C16/3409 , G11C16/3404 , G11C16/3445
摘要： A method of erase verifying and overerase verifying an array of flash memory cells by erase verifying each memory cell bit-by-bit in a memory array, overerase verifying each memory cell bit-by-bit in the memory array after each memory cell verifies as erased and again erase verifying each memory cell bit-by-bit in the memory array after each cell overerase verifies. The threshold voltage of each memory cell is compared to the threshold voltage of a reference memory cell and an overerase correction pulse is applied to the column in which the overerased memory cell is located.
摘要翻译：通过擦除存储器阵列中每个存储单元逐位擦除来擦除验证和过度验证闪速存储器单元的方法，每个存储器单元验证为在每个存储器单元中逐位验证每个存储器单元逐位擦除并再次擦除在每个单元过渡验证后对存储器阵列中的每个存储器单元进行逐位校验。将每个存储器单元的阈值电压与参考存储单元的阈值电压进行比较，并将高过度校正脉冲施加到高过度存储单元所在的列。

14. 发明申请

US20080062739A1 MEMORY ERASE MANAGEMENT SYSTEM 有权
标题翻译：内存删除管理系统
公开(公告)号：US20080062739A1
公开(公告)日：2008-03-13
申请号：US11470958
申请日：2006-09-07
申请人： Colin Bill , Mark McClain , Michael VanBuskirk
发明人： Colin Bill , Mark McClain , Michael VanBuskirk
IPC分类号： G11C7/00 , G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0097 , G11C2013/0076 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/79
摘要： A memory erase management system is provided, including providing a resistive change memory cell, coupling a first line to the resistive change memory cell, coupling a line buffer to the first line, providing a charge storage device coupled to the line buffer, and performing a single pulse erase of the resistive change memory cell by discharging a current from the charge storage device through the resistive change memory cell.
摘要翻译：提供了一种存储器擦除管理系统，包括提供电阻变化存储单元，将第一行耦合到电阻变化存储单元，将行缓冲器耦合到第一行，提供耦合到行缓冲器的电荷存储装置，以及执行通过从电荷存储装置通过电阻变化存储单元放电电流来对电阻变化存储单元进行单次脉冲擦除。

15. 发明授权

US07273766B1 Variable density and variable persistent organic memory devices, methods, and fabrication 有权
标题翻译：可变密度和可变持久性有机存储器件，方法和制造
公开(公告)号：US07273766B1
公开(公告)日：2007-09-25
申请号：US11034071
申请日：2005-01-12
申请人： Zhida Lan , Michael A. Van Buskirk , Tzu-Ning Fang , Colin Bill , John S. Ennals
发明人： Zhida Lan , Michael A. Van Buskirk , Tzu-Ning Fang , Colin Bill , John S. Ennals
IPC分类号： H01L21/00
CPC分类号： H01L27/285 , G11C11/5664 , G11C13/0014 , G11C13/0016 , G11C13/0035 , G11C13/0061 , G11C13/0069 , G11C14/00 , G11C2213/55 , G11C2213/71
摘要： An organic memory device comprising two electrodes having a selectively conductive decay media between the two electrodes provides a capability to control a persistence level for information stored in an organic memory cell. A resistive state of the cell controls a conductive decay rate of the cell. A high and/or low resistive state can provide a fast and/or slow rate of conductive decay. One aspect of the present invention can have a high resistive state equating to an exponential conductive decay rate. Another aspect of the present invention can have a low resistive state equating to a logarithmic conductive decay rate. Yet another aspect relates to control of an organic memory device by determining a power state and setting a resistive state of an organic memory cell based upon a current power state and/or an imminent power state.
摘要翻译：包括在两个电极之间具有选择性导电衰减介质的两个电极的有机存储器件提供了控制存储在有机存储器单元中的信息的持久性水平的能力。电池的电阻状态控制电池的导电衰减速率。高和/或低电阻状态可以提供快速和/或慢速的导电衰减。本发明的一个方面可以具有等于指数导电衰减速率的高电阻状态。本发明的另一方面可以具有等于对数导电衰减速率的低电阻状态。另一方面涉及通过基于当前功率状态和/或迫在眉睫的功率状态确定有功存储器单元的功率状态和设置电阻状态来控制有机存储器件。

16. 发明申请

US20060214183A1 Variable breakdown characteristic diode 有权
公开(公告)号：US20060214183A1
公开(公告)日：2006-09-28
申请号：US11087000
申请日：2005-03-22
申请人： David Gaun , Colin Bill , Swaroop Kaza
发明人： David Gaun , Colin Bill , Swaroop Kaza
IPC分类号： H01L29/00
CPC分类号： H01L51/0575 , B82Y10/00 , G11C11/5664 , G11C11/5692 , G11C13/0009 , G11C13/0014 , G11C13/0016 , G11C2213/11 , G11C2213/12 , G11C2213/15 , G11C2213/56 , G11C2213/71 , G11C2213/77 , H01L27/285
摘要： A memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes is disclosed. The controllably conductive media includes a passive layer made of super ionic material and an active layer. When an external stimuli, such as an applied electric field, is imposed upon the first and second electrode, ions move and dope and/or de-dope the polymer. The applied external stimuli used to dope the polymer is larger than an applied external stimuli to operate the memory cell. The polymer functions as a variable breakdown characteristic diode with electrical characteristics which are a consequence of the doping degree. The memory element may have a current limited read signal. Methods of making the memory devices/cells, methods of using the memory devices/cells, and devices such as computers, hand-held electronic devices and memory devices containing the memory cell(s) are also disclosed.

17. 发明申请

US20060139994A1 Method of programming, reading and erasing memory-diode in a memory-diode array 有权
标题翻译：在存储二极管阵列中编程，读取和擦除存储二极管的方法
公开(公告)号：US20060139994A1
公开(公告)日：2006-06-29
申请号：US11021958
申请日：2004-12-23
申请人： Colin Bill , Swaroop Kaza , Tzu-Ning Fang , Stuart Spitzer
发明人： Colin Bill , Swaroop Kaza , Tzu-Ning Fang , Stuart Spitzer
IPC分类号： G11C11/36
CPC分类号： G11C11/36
摘要： A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.
摘要翻译：存储器阵列包括第一和第二组导体和多个存储器二极管，每个存储器二极管以正向方向连接第一组的导体与第二组的导体。在选定的存储器二极管上施加电位，从正向上的较高电位到较低的电位，用于对所选存储二极管进行编程。在该期望的编程期间，阵列中的每个其它存储器二极管在其正向方向上提供低于其阈值电压的电位。每个存储器二极管的阈值电压可以通过在该存储器二极管上从相反方向上从较高电位向较低电位施加电位来建立。通过这样建立足够的阈值电压，并且通过选择适用于阵列导体的适当电位，避免了与电流泄漏和干扰有关的问题。

18. 发明申请

US20060049435A1 Vertical JFET as used for selective component in a memory array 审中-公开
标题翻译：用于存储器阵列中的选择性组件的垂直JFET
公开(公告)号：US20060049435A1
公开(公告)日：2006-03-09
申请号：US10935301
申请日：2004-09-07
申请人： Colin Bill , Michael Van Buskirk
发明人： Colin Bill , Michael Van Buskirk
IPC分类号： H01L29/80
CPC分类号： H01L27/10 , H01L27/098
摘要： Systems and methods are disclosed that facilitate providing a selective functionality to a polymer memory cell in a memory array while increasing device density in the memory cell array. A vertical JFET is described to which voltages can be selectively applied to control internal current flow there through, which in turn can be employed to manipulate the state of a polymer memory cell coupled to the vertical JFET. By mitigating gaps between gates, or wordlines, and drains of the vertical JFETs, feature size can be reduced to permit increased device density. Furthermore, vertical JFETs in the array can be coupled to gates on only two opposite sides, permitting the JFETs to be arranged without gate crossbars between them, further increasing device density. In this manner, the present invention provides switching characteristics to a memory cell and overcomes problematic bulkiness associated with conventional MOS devices.
摘要翻译：公开了系统和方法，其有助于提供存储器阵列中的聚合物存储器单元的选择性功能，同时增加存储器单元阵列中的器件密度。描述了可以选择性地施加电压以控制其中的内部电流的垂直JFET，其又可以用于操纵耦合到垂直JFET的聚合物存储器单元的状态。通过减轻栅极，字线和垂直JFET的漏极之间的间隙，可以减小特征尺寸以允许增加的器件密度。此外，阵列中的垂直JFET可以仅在两个相对的侧面上耦合到栅极，从而允许JFET布置成没有栅极交叉条之间，进一步增加器件密度。以这种方式，本发明向存储单元提供开关特性并且克服了与常规MOS器件相关的有问题的体积。

19. 发明授权

US06370065B1 Serial sequencing of automatic program disturb erase verify during a fast erase mode 有权
标题翻译：在快速擦除模式期间自动程序干扰擦除的串行排序校验
公开(公告)号：US06370065B1
公开(公告)日：2002-04-09
申请号：US09667347
申请日：2000-09-22
申请人： Feng Pan , Colin Bill
发明人： Feng Pan , Colin Bill
IPC分类号： G11C1604
CPC分类号： G11C16/3445 , G11C16/344
摘要： A method for serial sequencing the automatic disturb erase verify (APDEV) function during a multiple sector fast erase mode. The fast erase mode allows a memory device to erase several sectors of memory cells simultaneously. In order to minimize the time required to complete the APDEV and APDE functions, latches store for the address lines of the sector column positions. The APDEV function, therefore, can be performed serially on each of the sectors in the multiple sector group instead of all the sectors in the group simultaneously, thereby decreasing the amount of time required for the APDEV and APDE functions during the fast erase mode.
摘要翻译：一种在多扇区快速擦除模式下对自动干扰擦除验证（APDEV）功能进行串行排序的方法。快速擦除模式允许存储器件同时擦除存储器单元的多个扇区。为了最小化完成APDEV和APDE功能所需的时间，锁存器存储扇区列位置的地址线。因此，APDEV功能可以在多个扇区组中的每个扇区上而不是组中的所有扇区同时执行，从而减少快速擦除模式期间APDEV和APDE功能所需的时间量。

20. 发明授权

US07443712B2 Memory erase management system 有权
标题翻译：内存擦除管理系统
公开(公告)号：US07443712B2
公开(公告)日：2008-10-28
申请号：US11470958
申请日：2006-09-07
申请人： Colin Bill , Mark McClain , Michael VanBuskirk
发明人： Colin Bill , Mark McClain , Michael VanBuskirk
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0097 , G11C2013/0076 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/79
摘要： A memory erase management system is provided, including providing a resistive change memory cell, coupling a first line to the resistive change memory cell, coupling a line buffer to the first line, providing a charge storage device coupled to the line buffer, and performing a single pulse erase of the resistive change memory cell by discharging a current from the charge storage device through the resistive change memory cell.
摘要翻译：提供了一种存储器擦除管理系统，包括提供电阻变化存储单元，将第一行耦合到电阻变化存储单元，将行缓冲器耦合到第一行，提供耦合到行缓冲器的电荷存储装置，以及执行通过从电荷存储装置通过电阻变化存储单元放电电流来对电阻变化存储单元进行单次脉冲擦除。

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