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11. 发明授权

US4947227A Latch-up resistant CMOS structure 失效
标题翻译：防闩锁CMOS结构
公开(公告)号：US4947227A
公开(公告)日：1990-08-07
申请号：US776553
申请日：1985-09-16
申请人： Clarence W. Teng
发明人： Clarence W. Teng
IPC分类号： H01L27/08 , H01L21/762 , H01L21/8234 , H01L27/088 , H01L27/092
CPC分类号： H01L27/0921
摘要： A latch-up free CMOS structure and method of fabrication thereof is disclosed. A P-type substrate (40) is appropriately masked to form a plurality of sites in which isolated wells (50) are formed. A thermal oxide layer (56) is grown on the surface of each well (50), and a boron channel stop (62) implanted therearound. Polysilicon semiconductor material (68) is formed within each well, and implant doped to form an N-well (76) of material. The P-substrate (40) is planarized. PMOS transistors are formed within the oxide isolated N-wells (76), while NMOS transistors are formed in the P-substrate (40) outside the wells.
摘要翻译：公开了一种无闩锁CMOS结构及其制造方法。适当地掩蔽P型衬底（40）以形成其中形成隔离阱（50）的多个位置。在每个孔（50）的表面上生长热氧化物层（56），并且在其周围植入硼通道停止件（62）。在每个阱内形成多晶硅半导体材料（68），并且掺杂掺杂以形成材料的N阱（76）。 P基板（40）被平坦化。在氧化物隔离N阱（76）内形成PMOS晶体管，而在阱外部的P衬底（40）中形成NMOS晶体管。

12. 发明授权

US4916524A Dram cell and method 失效
标题翻译：戏剧细胞和方法
公开(公告)号：US4916524A
公开(公告)日：1990-04-10
申请号：US300467
申请日：1989-01-23
申请人： Clarence W. Teng , Robert R. Doering , Ashwin H. Shah
发明人： Clarence W. Teng , Robert R. Doering , Ashwin H. Shah
IPC分类号： H01L21/225 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L21/2254 , H01L27/10841
摘要： The described embodiments of the present invention provide structures, and a method for fabricating those structures, which include a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide when opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is then formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench. Conductive material is then formed inside the open portion of the upper portion of the trench thereby forming a transistor connecting the upper plate of the storage capacitor to a drain region on the surface of the semiconductor substrate.
摘要翻译：本发明的所描述的实施例提供了包括形成在单个沟槽内的存储单元的结构和制造这些结构的方法。在半导体衬底的表面形成沟槽。沟槽的底部填充有多晶硅以形成存储电容器的一个板。该基板用作电容器的另一个板。然后用绝缘材料如二氧化硅填充沟槽的剩余部分。然后当将侧壁的一部分和沟槽的顶部部分向下切割到多晶电容器板时，将图案蚀刻到二氧化硅中。然后在多晶电容器板和衬底之间形成接触。掺杂原子通过接触扩散以在沟槽的侧壁上形成源区。通过氧化形成栅极绝缘体，并且在与沟槽的口相邻的沟槽的表面处形成漏极。然后，在沟槽上部的开口部分形成导电材料，从而形成将存储电容器的上板连接到半导体衬底的表面上的漏极区域的晶体管。

13. 发明授权

US4842675A Integrated circuit isolation process 失效
标题翻译：集成电路隔离过程
公开(公告)号：US4842675A
公开(公告)日：1989-06-27
申请号：US882732
申请日：1986-07-07
申请人： Richard A. Chapman , Clarence W. Teng
发明人： Richard A. Chapman , Clarence W. Teng
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/76235 , Y10S148/05
摘要： A multiple recess isolation technology avoids stress induced defects while providing a substantially planar surface. A silicon substrate (10) is patterned and etched, creating active moat regions (18) and recesses (20a-b and 21a-b). The recesses are filled with oxide by growing a field oxide (40) in wide recessed regions (21) using a LOCOS process, while depositing a planarization field oxide (44) in narrow recessed regions (20). After etching the structure to obtain a planar surface, standard procedures are used to fabricate the active devices. The process uses a single photolithographic masking step and results in only a very small loss of the width electrically active regions.
摘要翻译：多凹陷隔离技术避免了应力诱发的缺陷，同时提供了基本平坦的表面。对硅衬底（10）进行构图和蚀刻，形成活动的护套区域（18）和凹槽（20a-b和21a-b）。通过使用LOCOS工艺在宽的凹陷区域（21）中生长场氧化物（40），同时在窄的凹陷区域（20）中沉积平坦化场氧化物（44）来使凹陷填充氧化物。在蚀刻结构以获得平坦表面之后，使用标准程序来制造有源器件。该过程使用单个光刻掩模步骤，并且导致宽度电活性区域的非常小的损失。

14. 发明授权

US4660278A Process of making IC isolation structure 失效
标题翻译：制造IC隔离结构的过程
公开(公告)号：US4660278A
公开(公告)日：1987-04-28
申请号：US749952
申请日：1985-06-26
申请人： Clarence W. Teng
发明人： Clarence W. Teng
IPC分类号： H01L21/76 , H01L21/20 , H01L21/74 , H01L21/762 , H01L21/302
CPC分类号： H01L21/74 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/76294
摘要： Using a structure according to one embodiment of the present invention, active elements in integrated circuitry may be completely isolated from other elements in the integrated circuitry by silicon dioxide regions surrounding the sides of the region containing the active element and a buried diffusion beneath the active element extending to all sides of the isolating silicon dioxide regions.In one embodiment of the present invention, an isolation structure is fabricated by etching a silicon substrate to remove the silicon from the entire region occupied by the isolated active area and the isolation structure of this embodiment of the invention. A conformal layer of silicon dioxide, or other dielectric material, is then deposited on the surface of the silicon substrate. The conformal silicon dioxide layer is then anisotropically etched to remove the silicon dioxide on the bottom of the isolation region but still provide a sidewall region of silicon dioxide on the sides of the isolation region. The bottom of the isolation region is then implanted with dopant ions to provide a depletion region in the bottom of the isolation region. Crystalline silicon is then grown from the base of the isolation region to form the isolation region flush with the surface of the substrate using selective epitaxial growth.
摘要翻译：使用根据本发明的一个实施例的结构，集成电路中的有源元件可以通过围绕包含有源元件的区域的侧面的二氧化硅区域和在有源元件下方的埋入扩散与集成电路中的其它元件完全隔离延伸到隔离二氧化硅区域的所有侧面。在本发明的一个实施例中，通过蚀刻硅衬底以从本发明的该实施例的隔离有源区域和隔离结构占据的整个区域中除去硅来制造隔离结构。然后将二氧化硅或其它电介质材料的保形层沉积在硅衬底的表面上。然后各向异性蚀刻保形二氧化硅层以去除隔离区域的底部上的二氧化硅，但是仍然在隔离区域的侧面上提供二氧化硅的侧壁区域。然后用掺杂剂离子注入隔离区的底部，以在隔离区的底部提供耗尽区。然后从隔离区域的基底生长晶体硅，以使用选择性外延生长形成与衬底的表面齐平的隔离区域。

15. 发明授权

US4580330A Integrated circuit isolation 失效
标题翻译：集成电路隔离
公开(公告)号：US4580330A
公开(公告)日：1986-04-08
申请号：US621019
申请日：1984-06-15
申请人： Gordon P. Pollack , Clarence W. Teng , William R. Hunter , Christopher Slawinski , Robert R. Doering
发明人： Gordon P. Pollack , Clarence W. Teng , William R. Hunter , Christopher Slawinski , Robert R. Doering
IPC分类号： H01L29/78 , H01L21/32 , H01L21/76 , H01L21/762 , H01L29/06
CPC分类号： H01L29/0638 , H01L21/32 , H01L21/76232 , Y10S148/05
摘要： An integrated circuit isolation technology wherein the nitride-sidewall methods of the prior art are improved by performing an undercut and backfill before the second nitride (the sidewall nitride which prevents encroachment) is added to the first nitride (which covers the moat areas). Thus, the butt joint between the two nitrides is made more secure, and localized bird's-beaking at the butt joint between the moat nitride and the sidewall nitride does not occur.
摘要翻译：一种集成电路隔离技术，其中通过在将第二氮化物（防止侵入的侧壁氮化物）添加到第一氮化物（覆盖护城河区域）之前执行底切和回填来改进现有技术的氮化物 - 侧壁方法。因此，使两个氮化物之间的对接更牢固，并且不会发生在护环氮化物和侧壁氮化物之间的对接接合处的局部鸟鸣。

16. 发明授权

US5352913A Dynamic memory storage capacitor having reduced gated diode leakage 失效
标题翻译：具有降低的门控二极管泄漏的动态存储器存储电容器
公开(公告)号：US5352913A
公开(公告)日：1994-10-04
申请号：US204909
申请日：1994-03-02
申请人： Gishi Chung , William R. McKee , Clarence W. Teng
发明人： Gishi Chung , William R. McKee , Clarence W. Teng
IPC分类号： H01L27/10 , H01L21/02 , H01L21/8242 , H01L27/108 , H01L29/68 , H01L29/92
CPC分类号： H01L27/10861 , H01L28/40
摘要： A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. Trenches are etched into a face of a body of semiconductor material. Storage nodes surrounding the trenches are created. A polysilicon layer is formed on the trench walls. A storage dielectric layer is formed on the trench walls, adjacent to the layer of polysilicon on the trench walls, so that the layer of polysilicon on the trench walls lies between the storage dielectric layer and the storage node. The layer of polysilicon on the trench walls reduces leakage current from the storage node. A trench type field plate isolated random access memory cell structure is also disclosed.
摘要翻译：公开了一种在沟槽电容器型场板隔离型动态随机存取存储器件中降低栅极二极管泄漏的方法。沟槽蚀刻成半导体材料体的表面。创建围绕沟槽的存储节点。在沟槽壁上形成多晶硅层。在与沟槽壁上的多晶硅层相邻的沟槽壁上形成存储电介质层，使得沟槽壁上的多晶硅层位于存储介电层和存储节点之间。沟槽壁上的多晶硅层减少了来自存储节点的泄漏电流。还公开了沟槽型场板隔离随机存取存储单元结构。

17. 发明授权

US5225363A Trench capacitor DRAM cell and method of manufacture 失效
标题翻译：沟槽电容器DRAM单元及其制造方法
公开(公告)号：US5225363A
公开(公告)日：1993-07-06
申请号：US823804
申请日：1992-01-15
申请人： Bert R. Riemenschneider , Allan T. Mitchell , Clarence W. Teng
发明人： Bert R. Riemenschneider , Allan T. Mitchell , Clarence W. Teng
IPC分类号： H01L27/108
CPC分类号： H01L27/10829
摘要： A plurality of trenches (26, 28) of a DRAM cell array formed in a (P-) epitaxial layer (11) and a silicon substrate (12), and storage layers (38, 40) are grown on the sidewalls (34, 36) and bottom (not shown) of the trenches (26, 28). Highly doped polysilicon capacitor electrodes (42, 44) are formed in the trenches (26, 28). Sidewall oxide filaments (50, 54) and in situ doped sidewall conductive filaments (66, 68) are formed and thermal cycles are used to diffuse dopant from sidewall conductive filaments (66, 68) into upper sidewall portions (62, 64) to form diffused source regions (70, 72) of pass gate transistors (90) for each cell.
摘要翻译：形成在（P-）外延层（11）和硅衬底（12）中的DRAM单元阵列的多个沟槽（26,28）和存储层（38,40）生长在侧壁 36）和底部（未示出）的沟槽（26,28）。在沟槽（26,28）中形成高掺杂多晶硅电容器电极（42,44）。形成侧壁氧化物细丝（50,54）和原位掺杂的侧壁导电细丝（66,68），并且使用热循环来将掺杂剂从侧壁导电细丝（66,68）扩散到上侧壁部分（62,64）中以形成用于每个单元的通过栅极晶体管（90）的扩散源极区（70,72）。

18. 发明授权

US5156992A Process for forming poly-sheet pillar transistor DRAM cell 失效
标题翻译：多片立柱晶体管DRAM单元的形成工艺
公开(公告)号：US5156992A
公开(公告)日：1992-10-20
申请号：US720542
申请日：1991-06-25
申请人： Clarence W. Teng , Robert R. Doering
发明人： Clarence W. Teng , Robert R. Doering
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10876 , H01L27/10841
摘要： A memory cell comprises a semiconductor pillar and an insulator on a sidewall of the pillar. A conductive capacitor of the memory cell comprises a first electrode adjacent the insulator. A transistor of the memory cell is formed in the pillar and comprises a first source/drain region, a gate, and a second source/drain region coupled to the first electrode.
摘要翻译：存储单元包括在柱的侧壁上的半导体柱和绝缘体。存储单元的导电电容器包括邻近绝缘体的第一电极。存储单元的晶体管形成在柱中，并且包括耦合到第一电极的第一源极/漏极区域，栅极和第二源极/漏极区域。

19. 发明授权

US5057887A High density dynamic RAM cell 失效
标题翻译：高密度动态RAM单元
公开(公告)号：US5057887A
公开(公告)日：1991-10-15
申请号：US366801
申请日：1989-06-14
申请人： Masaaki Yashiro , Shigeki Morinaga , Clarence W. Teng
发明人： Masaaki Yashiro , Shigeki Morinaga , Clarence W. Teng
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/68 , H01L29/06 , H01L29/40
CPC分类号： H01L27/10829 , Y10S257/90
摘要： The described embodiments of the present invention provide a memory cell and method for fabricating that memory cell and memory array including the cell. The memory cell is a trench capacitor type having a transistor (1-1-2) formed on the surface of a major face of a substrate (16) and having a capacitor (2-1-2) formed in the substrate around the periphery of a trench. The capacitor and transistor are connected by a buried, heavily doped region (26) having the opposite conductivity type from the substrate. A doped storage area (24) having the same doping type as the buried doped region surrounds the trench. A field plate (30) is formed in the trench separated from the storage region by a dielectric layer (32). The field plate extends onto the isolation areas between memory cells thus providing isolation between cells using a minimum of surface area. A self-aligned process is used to form the source (14) and drain (12) for the pass gate transistor and automatic connection between the source of the transistor and the buried doping layer is made by the buried N+ layer. A sidewall silicon nitride passivation filament (38) is formed to protect the sidewalls of the interlevel insulator region between the first (30) and second (3-3, 3-4) polycrystalline silicon layers.

20. 发明授权

US4987093A Through-field implant isolated devices and method 失效
标题翻译：通过野外植入隔离装置和方法
公开(公告)号：US4987093A
公开(公告)日：1991-01-22
申请号：US426824
申请日：1989-10-24
申请人： Clarence W. Teng , Roger A. Haken
发明人： Clarence W. Teng , Roger A. Haken
IPC分类号： H01L21/265 , H01L21/762
CPC分类号： H01L21/2652 , H01L21/76216
摘要： Preferred embodiments include channel stop implants for CMOS devices by through field boron implants (152) after the field oxide (144, 145) has been grown and with the implant depth determined by the thin portions of the field oxide (145). Junction (154) breakdown is preserved by channeling the implant (152) to penetrate far below the junctions (154).
摘要翻译：优选实施例包括在场氧化物（144,145）已经生长之后并且通过场氧化物（145）的薄部分确定的注入深度的通过场硼注入（152）的CMOS器件的沟道停止注入。通过将植入物（152）引导穿过接合点（154）的下方来保护结（154）分解。

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