专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20080119044A1 SYSTEMS AND METHODS FOR BACK END OF LINE PROCESSING OF SEMICONDUCTOR CIRCUITS 审中-公开
标题翻译：半导体电路线路处理后端系统及方法
公开(公告)号：US20080119044A1
公开(公告)日：2008-05-22
申请号：US11562834
申请日：2006-11-22
申请人： Tuung Luoh , Chi-Tung Huang , Kuang-Chao Chen , Candy Jiang
发明人： Tuung Luoh , Chi-Tung Huang , Kuang-Chao Chen , Candy Jiang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76864 , H01L21/76877
摘要： A BEOL manufacturing process for forming a via on a semiconductor wafer comprises depositing a portion of a first metal adhesion layer within a patterned via hole, followed by a cooling step. The cooling step is then followed by formation of the remainder of the first metal adhesion layer and formation of a second metal adhesion layer within the patterned via hole. This process of forming the remaining portion of the first metal adhesion layer can be referred to as a load, unload, load (LUL) process. By using a LUL process, thermal processing is minimized, which reduces Al extrusion at the via interfaces.
摘要翻译：用于在半导体晶片上形成通孔的BEOL制造方法包括在图案化的通孔内沉积第一金属粘附层的一部分，接着进行冷却步骤。然后冷却步骤之后形成第一金属粘合层的其余部分，并在图案化的通孔内形成第二金属粘合层。形成第一金属粘合层的剩余部分的过程可以被称为负载，卸载，负载（LUL）过程。通过使用LUL工艺，热处理被最小化，这减少了通孔界面处的Al挤压。

12. 发明授权

US06688969B2 Method for planarizing a dielectric layer of a flash memory device 有权
标题翻译：平面化闪存器件的电介质层的方法
公开(公告)号：US06688969B2
公开(公告)日：2004-02-10
申请号：US10165655
申请日：2002-06-07
申请人： Chi-Tung Huang
发明人： Chi-Tung Huang
IPC分类号： B24B100
CPC分类号： H01L27/115 , B24B37/044 , B24B37/245 , B24B37/26 , C09G1/04 , H01L21/31053 , H01L27/1122 , H01L27/11521
摘要： A method for planarizing the dielectric layer of a flash memory device, wherein the method is applied on substrate of a flash memory device having a plurality of gate structures formed thereon and a protective layer is formed on the gate structures. A dielectric layer is formed on the substrate, filling the space between the gate structures and covering the protective layer. Using the protective layer as a polishing endpoint layer, a fixed base and a polishing slurry that does not contain metal ions are used to chemical mechanically polish and to planarize the dielectric layer. The fixed base includes a base and evenly distributed polishing abrasives fixed onto the base.
摘要翻译：一种用于对闪速存储器件的介电层进行平坦化的方法，其中将该方法应用于其上形成有多个栅极结构的闪存器件的衬底上，并且在栅极结构上形成保护层。在基板上形成电介质层，填充栅极结构之间的空间并覆盖保护层。使用保护层作为抛光终点层，使用不含金属离子的固定基底和抛光浆料进行化学机械抛光和平坦化介电层。固定底座包括固定在基座上的底座和均匀分布的抛光磨料。

13. 发明授权

US06521922B1 Passivation film on a semiconductor wafer 有权
标题翻译：半导体晶片上的钝化膜
公开(公告)号：US06521922B1
公开(公告)日：2003-02-18
申请号：US09514261
申请日：2000-02-28
申请人： Chi-Tung Huang , Wan-Yi Liu
发明人： Chi-Tung Huang , Wan-Yi Liu
IPC分类号： H01L2972
CPC分类号： H01L21/76832 , H01L21/76837
摘要： The present invention provides a passivation film on a semiconductor wafer. The semiconductor wafer comprises a dielectric layer and a patterned conductive layer on the dielectric layer. The passivation film comprises a high density plasma (HDP) oxide layer positioned on the surface of the conductive layer and on the surface of the dielectric layer that is not covered by the conductive layer, a silicon nitride layer positioned on the HDP oxide layer, and a water-resistant layer positioned on the silicon nitride layer. The HDP oxide layer possesses good gap filling abilities to fill the spaces inside the conductive layer.
摘要翻译：本发明提供半导体晶片上的钝化膜。半导体晶片包括电介质层和介电层上的图案化导电层。钝化膜包括位于导电层的表面上的介电层表面上未被导电层覆盖的高密度等离子体（HDP）氧化物层，位于HDP氧化物层上的氮化硅层，以及位于氮化硅层上的防水层。 HDP氧化物层具有良好的间隙填充能力以填充导电层内的空间。

14. 发明授权

US06509249B1 Method of fabricating shallow trench isolation 有权
标题翻译：浅沟槽隔离的制作方法
公开(公告)号：US06509249B1
公开(公告)日：2003-01-21
申请号：US10158748
申请日：2002-05-28
申请人： Yuhturng Liu , Chi-Tung Huang
发明人： Yuhturng Liu , Chi-Tung Huang
IPC分类号： G01R3126
CPC分类号： H01L21/76232
摘要： A method of fabricating a shallow trench isolation structure. A pad oxide layer, a mask layer, a dielectric anti-reflection coating layer and a cap oxide layer are formed on a substrate sequentially. A trench is formed in the substrate. A liner oxide layer is formed along a surface of the trench. An isolation layer is formed over the substrate to fill the trench. Using the mask layer as a polishing endpoint, the insulation layer, the dielectric anti-reflection coating layer and the cap oxide layer over the mask layer are removed. The thickness of the mask layer is controlled within a first fixed range, and the thickness of the dielectric anti-reflection coating layer is controlled, within a second fixed range, such that the light source of the optical endpoint detection system can produce a maximum reflected light signal. The mask layer and the pad oxide layer are then removed.
摘要翻译：一种制造浅沟槽隔离结构的方法。在衬底上依次形成衬垫氧化物层，掩模层，电介质抗反射涂层和帽氧化物层。在衬底中形成沟槽。沿着沟槽的表面形成衬里氧化物层。在衬底上形成隔离层以填充沟槽。使用掩模层作为抛光终点，除去掩模层上的绝缘层，电介质抗反射涂层和盖氧化物层。将掩模层的厚度控制在第一固定范围内，并且在第二固定范围内控制电介质防反射涂层的厚度，使得光学终点检测系统的光源可以产生最大反射光信号。然后去除掩模层和焊盘氧化物层。

15. 发明申请

US20080119042A1 SYSTEMS AND METHODS FOR BACK END OF LINE PROCESSING OF SEMICONDUCTOR CIRCUITS 有权
标题翻译：半导体电路线路处理后端系统及方法
公开(公告)号：US20080119042A1
公开(公告)日：2008-05-22
申请号：US11847135
申请日：2007-08-29
申请人： Tuung Luoh , Chi-Tung Huang , Kuang-Chao Chen , Candy Jiang
发明人： Tuung Luoh , Chi-Tung Huang , Kuang-Chao Chen , Candy Jiang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76864 , H01L21/76877
摘要： A BEOL manufacturing process for forming a via process between two metal lines on a semiconductor wafer comprises depositing a portion of a first metal adhesion layer within a patterned via hole, followed by a cooling step. The cooling step is then followed by formation of the remainder of the first metal adhesion layer and formation of a second metal adhesion layer within the patterned via hole. This process of forming the remaining portion of the first metal adhesion layer can be referred to as a wafer load, unload, load (LUL) process. By using a LUL process, thermal history is minimized, which reduces Al extrusion at the via interfaces.
摘要翻译：用于在半导体晶片上的两个金属线之间形成通孔工艺的BEOL制造工艺包括在图案化的通孔内沉积第一金属粘附层的一部分，接着进行冷却步骤。然后冷却步骤之后形成第一金属粘合层的其余部分，并在图案化的通孔内形成第二金属粘合层。形成第一金属粘合层的剩余部分的这个过程可以被称为晶片负载，卸载，负载（LUL）过程。通过使用LUL工艺，可以最大限度地减少热历史，从而减少通孔界面处的Al挤压。

16. 发明申请

US20070161204A1 Methods for metal ARC layer formation 有权
标题翻译：金属ARC层形成方法
公开(公告)号：US20070161204A1
公开(公告)日：2007-07-12
申请号：US11329553
申请日：2006-01-11
申请人： Hsing-Hua Chiu , Tuung Luoh , Chi-Tung Huang , Kuang-Chao Chen
发明人： Hsing-Hua Chiu , Tuung Luoh , Chi-Tung Huang , Kuang-Chao Chen
IPC分类号： H01L21/76
CPC分类号： H01L23/53223 , H01L21/0276 , H01L21/2855 , H01L21/32051 , H01L21/32139 , H01L2924/0002 , Y10S438/952 , H01L2924/00
摘要： A process for forming an ARC layer in the fabrication of a semiconductor device comprises forming a modified ARC layer that increases the resistance to crown defects and bridging and also provides better adhesion for the ARC layer with the underlying metal layer. The modified ARC layer can comprise two titanium nitride ARC layers, a titanium nitride/titanium/titanium nitride sandwich structure, a modified titanium nitride layer, or an extended thickness titanium nitride layer.
摘要翻译：在制造半导体器件中形成ARC层的方法包括形成改进的ARC层，其增加了对冠部缺陷和桥接的抵抗性，并且还为具有下面的金属层的ARC层提供了更好的附着力。经修改的ARC层可以包括两个氮化钛ARC层，氮化钛/钛/氮化钛夹层结构，改性氮化钛层或延伸厚度的氮化钛层。

17. 发明申请

US20060292774A1 Method for preventing metal line bridging in a semiconductor device 审中-公开
标题翻译：防止半导体器件中的金属线桥接的方法
公开(公告)号：US20060292774A1
公开(公告)日：2006-12-28
申请号：US11166230
申请日：2005-06-27
申请人： Lee-Jen Chen , Chin-Ta Su , Chi-Tung Huang
发明人： Lee-Jen Chen , Chin-Ta Su , Chi-Tung Huang
IPC分类号： H01L21/8234
CPC分类号： H01L21/76834 , H01L21/76832
摘要： A method for forming a semiconductor device includes providing a substrate, providing aluminum metal lines on the substrate, forming a barrier layer over the aluminum metal lines, and forming a silicon-rich dielectric layer over the barrier layer. An inter-metal dielectric (IMD) layer may be formed to cover at least a portion of the silicon-rich dielectric layer.
摘要翻译：一种形成半导体器件的方法包括提供衬底，在衬底上提供铝金属线，在铝金属线上形成阻挡层，并在阻挡层上形成富硅电介质层。可以形成金属间电介质（IMD）层以覆盖富硅电介质层的至少一部分。

18. 发明授权

US06407454B1 Inter-metal dielectric layer 有权
标题翻译：金属介电层
公开(公告)号：US06407454B1
公开(公告)日：2002-06-18
申请号：US09712727
申请日：2000-11-14
申请人： Ping-Yi Chang , Pei-Ren Jeng , Chi-Tung Huang
发明人： Ping-Yi Chang , Pei-Ren Jeng , Chi-Tung Huang
IPC分类号： H01L2328
CPC分类号： H01L21/02131 , C23C16/401 , H01L21/02274 , H01L21/02362 , H01L21/31629 , H01L21/76819 , H01L21/76837 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing dielectric layers between metal parts by forming fluorine silicate glass by high density plasma deposition using radio frequency power of low bias voltage. The method includes filling in a gap with fluorine silicate glass by high density plasma deposition with slower rate of deposition and radio frequency power of high bias voltage, and then using fluorine silicate glass deposited with fast rate of deposition and radio frequency power of no or low bias voltage as a sacrificial layer, and being made plane by a chemical-mechanic polishing CMP.
摘要翻译：一种通过使用低偏压的射频功率通过高密度等离子体沉积形成氟硅酸盐玻璃来在金属部件之间制造电介质层的方法。该方法包括以较低的沉积速率和较高的偏置电压的射频功率通过高密度等离子体沉积与氟硅酸盐玻璃填充间隙，然后使用沉积速度较快的无硅或低频的氟硅酸盐玻璃偏置电压作为牺牲层，并通过化学机械抛光CMP制成平面。

19. 发明授权

US08003519B2 Systems and methods for back end of line processing of semiconductor circuits 有权
标题翻译：半导体电路线路处理后端系统及方法
公开(公告)号：US08003519B2
公开(公告)日：2011-08-23
申请号：US11847135
申请日：2007-08-29
申请人： Tuung Luoh , Chi-Tung Huang , Kuang-Chao Chen , Candy Jiang
发明人： Tuung Luoh , Chi-Tung Huang , Kuang-Chao Chen , Candy Jiang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76864 , H01L21/76877
摘要： A BEOL manufacturing process for forming a via process between two metal lines on a semiconductor wafer comprises depositing a portion of a first metal adhesion layer within a patterned via hole, followed by a cooling step. The cooling step is then followed by formation of the remainder of the first metal adhesion layer and formation of a second metal adhesion layer within the patterned via hole. This process of forming the remaining portion of the first metal adhesion layer can be referred to as a wafer load, unload, load (LUL) process. By using a LUL process, thermal history is minimized, which reduces Al extrusion at the via interfaces.
摘要翻译：用于在半导体晶片上的两个金属线之间形成通孔工艺的BEOL制造工艺包括在图案化的通孔内沉积第一金属粘附层的一部分，接着进行冷却步骤。然后冷却步骤之后形成第一金属粘合层的其余部分，并在图案化的通孔内形成第二金属粘合层。形成第一金属粘合层的剩余部分的这个过程可以被称为晶片负载，卸载，负载（LUL）过程。通过使用LUL工艺，可以最大限度地减少热历史，从而减少通孔界面处的Al挤压。

20. 发明授权

US07498257B2 Methods for metal ARC layer formation 有权
标题翻译：金属ARC层形成方法
公开(公告)号：US07498257B2
公开(公告)日：2009-03-03
申请号：US11329553
申请日：2006-01-11
申请人： Hsing-Hua Chiu , Tuung Luoh , Chi-Tung Huang , Kuang-Chao Chen
发明人： Hsing-Hua Chiu , Tuung Luoh , Chi-Tung Huang , Kuang-Chao Chen
IPC分类号： H01L21/4763
CPC分类号： H01L23/53223 , H01L21/0276 , H01L21/2855 , H01L21/32051 , H01L21/32139 , H01L2924/0002 , Y10S438/952 , H01L2924/00
摘要： A process for forming an ARC layer in the fabrication of a semiconductor device comprises forming a modified ARC layer that increases the resistance to crown defects and bridging and also provides better adhesion for the ARC layer with the underlying metal layer. The modified ARC layer can comprise two titanium nitride ARC layers, a titanium nitride/titanium/titanium nitride sandwich structure, a modified titanium nitride layer, or an extended thickness titanium nitride layer.
摘要翻译：在制造半导体器件中形成ARC层的方法包括形成改进的ARC层，其增加了对冠部缺陷和桥接的抵抗性，并且还为具有下面的金属层的ARC层提供了更好的附着力。经修改的ARC层可以包括两个氮化钛ARC层，氮化钛/钛/氮化钛夹层结构，改性氮化钛层或延伸厚度的氮化钛层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式