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11. 发明授权

US08363450B2 Hierarchical cross-point array of non-volatile memory 有权
标题翻译：非易失性存储器的分层交叉点阵列
公开(公告)号：US08363450B2
公开(公告)日：2013-01-29
申请号：US13280109
申请日：2011-10-24
申请人： Chulmin Jung , Yong Lu , Insik Jin , YoungPil Kim , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Insik Jin , YoungPil Kim , Harry Hongyue Liu
IPC分类号： G11C11/00
CPC分类号： A01H6/14 , A01H5/02
摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.
摘要翻译：一种用于从非易失性存储单元读取数据的方法和装置。在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列。提供了选择电路，其能够在禁用第二存储单元块的同时激活存储器单元的第一块。此外，提供一种读取电路，其能够通过对与第一存储器块相对应的块选择元件编程第一电阻状态，以减小的漏电流来读取存储器单元的第一块中的预定存储器单元的逻辑状态同时将第二电阻状态编程到对应于存储器单元的第二块的块选择元件。

12. 发明授权

US08248836B2 Non-volatile memory cell stack with dual resistive elements 有权
标题翻译：具有双电阻元件的非易失性存储单元堆叠
公开(公告)号：US08248836B2
公开(公告)日：2012-08-21
申请号：US12501751
申请日：2009-07-13
申请人： Insik Jin , YoungPil Kim , Ming Sun , Chulmin Jung , Venugopalan Vaithyanathan , Nurul Amin , Wei Tian , Yong Lu
发明人： Insik Jin , YoungPil Kim , Ming Sun , Chulmin Jung , Venugopalan Vaithyanathan , Nurul Amin , Wei Tian , Yong Lu
IPC分类号： G11C11/00 , G11C11/14 , G11C7/00
CPC分类号： G11C11/16 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2213/76
摘要： A non-volatile memory cell and method of use thereof. In some embodiments, an individually programmable resistive sense memory (RSM) element is connected in series with a programmable metallization cell (PMC) switching element. In operation, while the switching element is programmed to a first resistive state, no current passes through the RSM element and while a second resistive state is programmed to the RSM element, current passes through the RSM element.
摘要翻译：一种非易失性存储单元及其使用方法。在一些实施例中，独立可编程电阻感测存储器（RSM）元件与可编程金属化单元（PMC）开关元件串联连接。在操作中，当开关元件被编程为第一电阻状态时，没有电流通过RSM元件，并且当第二电阻状态被编程到RSM元件时，电流通过RSM元件。

13. 发明申请

US20120199915A1 Patterning Embedded Control Lines for Vertically Stacked Semiconductor Elements 审中-公开
标题翻译：用于垂直堆叠半导体元件的嵌入式控制线图案化
公开(公告)号：US20120199915A1
公开(公告)日：2012-08-09
申请号：US13446462
申请日：2012-04-13
申请人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
发明人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
IPC分类号： H01L27/105
CPC分类号： H01L27/101 , H01L27/228 , H01L27/2454 , H01L27/2463 , H01L43/08 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1675
摘要： The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
摘要翻译：本发明一般涉及用于垂直堆叠的半导体元件的具有嵌入式（底侧）控制线的装置。根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

14. 发明授权

US08098507B2 Hierarchical cross-point array of non-volatile memory 有权
标题翻译：非易失性存储器的分层交叉点阵列
公开(公告)号：US08098507B2
公开(公告)日：2012-01-17
申请号：US12502199
申请日：2009-07-13
申请人： Chulmin Jung , Yong Lu , Insik Jin , YoungPil Kim , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Insik Jin , YoungPil Kim , Harry Hongyue Liu
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C2213/76 , G11C2213/77 , G11C2213/78 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1266 , H01L45/147
摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.
摘要翻译：一种用于从非易失性存储单元读取数据的方法和装置。在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列。提供了选择电路，其能够在禁用第二存储单元块的同时激活存储器单元的第一块。此外，提供一种读取电路，其能够通过对与第一存储器块相对应的块选择元件编程第一电阻状态，以减小的漏电流来读取存储器单元的第一块中的预定存储器单元的逻辑状态同时将第二电阻状态编程到对应于存储器单元的第二块的块选择元件。

15. 发明申请

US20110170335A1 Vertical Non-Volatile Switch with Punchthrough Access and Method of Fabrication Therefor 审中-公开
标题翻译：具有Punchthrough访问的垂直非易失性开关及其制造方法
公开(公告)号：US20110170335A1
公开(公告)日：2011-07-14
申请号：US13071882
申请日：2011-03-25
申请人： Maroun Georges Khoury , Hyung-Kyu Lee , Peter Nicholas Manos , Chulmin Jung , YoungPil Kim
发明人： Maroun Georges Khoury , Hyung-Kyu Lee , Peter Nicholas Manos , Chulmin Jung , YoungPil Kim
IPC分类号： G11C11/34
CPC分类号： H01L27/101 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C2213/79 , H01L29/8618
摘要： A semiconductor device for accessing non-volatile memory cell is provided. In some embodiments, the semiconductor device has a vertical stack of semiconductor layers including a source, a drain, and a well. An application of a drain-source bias voltage to the semiconductor device generates a punchthrough mechanism across the well to initiate a flow of current between the source and the drain.
摘要翻译：提供一种用于访问非易失性存储单元的半导体器件。在一些实施例中，半导体器件具有包括源极，漏极和阱的半导体层的垂直堆叠。向半导体器件施加漏极 - 源极偏置电压在阱上产生穿透机构以引发源极和漏极之间的电流。

16. 发明授权

US07961526B2 Power saving sensing scheme for solid state memory 有权
标题翻译：固态存储器的省电感测方案
公开(公告)号：US07961526B2
公开(公告)日：2011-06-14
申请号：US12502932
申请日：2009-07-14
申请人： Chulmin Jung , Kang Yong Kim
发明人： Chulmin Jung , Kang Yong Kim
IPC分类号： G11C7/00
CPC分类号： G11C8/12 , G11C7/103 , G11C8/18
摘要： Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device.
摘要翻译：公开了诸如涉及固态存储器件的方法和装置。一种这样的方法包括选择存储器阵列中的多个存储器单元。确定存储在所选择的多个存储单元中的多个数据位的状态。在确定多个数据位的状态时，多个数据位的一部分被感测得比其他数据位更快。顺序提供多个数据位作为输出。在一个实施例中，多个数据位的部分包括存储器件的顺序输出的第一位。

17. 发明申请

US20110007548A1 Hierarchical Cross-Point Array of Non-Volatile Memory 有权
标题翻译：非易失性存储器的分层交叉点阵列
公开(公告)号：US20110007548A1
公开(公告)日：2011-01-13
申请号：US12502199
申请日：2009-07-13
申请人： Chulmin Jung , Yong Lu , Insik Jin , YoungPil Kim , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Insik Jin , YoungPil Kim , Harry Hongyue Liu
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00
CPC分类号： G11C13/003 , G11C2213/76 , G11C2213/77 , G11C2213/78 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1266 , H01L45/147
摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.
摘要翻译：一种用于从非易失性存储单元读取数据的方法和装置。在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列。提供了选择电路，其能够在禁用第二存储单元块的同时激活存储器单元的第一块。此外，提供一种读取电路，其能够通过对与第一存储器块相对应的块选择元件编程第一电阻状态，以减小的漏电流来读取存储器单元的第一块中的预定存储器单元的逻辑状态同时将第二电阻状态编程到对应于存储器单元的第二块的块选择元件。

18. 发明申请

US20110007545A1 Non-Volatile Memory Cell Stack with Dual Resistive Elements 有权
标题翻译：具有双电阻元件的非易失性存储单元堆栈
公开(公告)号：US20110007545A1
公开(公告)日：2011-01-13
申请号：US12501751
申请日：2009-07-13
申请人： Insik Jin , YoungPil Kim , Ming Sun , Chulmin Jung , Venugopalan Vaithyanathan , Nurul Amin , Wei Tian , Yong Lu
发明人： Insik Jin , YoungPil Kim , Ming Sun , Chulmin Jung , Venugopalan Vaithyanathan , Nurul Amin , Wei Tian , Yong Lu
IPC分类号： G11C11/00 , G11C11/14 , G11C7/00
CPC分类号： G11C11/16 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2213/76
摘要： A non-volatile memory cell and method of use thereof. In some embodiments, an individually programmable resistive sense memory (RSM) element is connected in series with a programmable metallization cell (PMC) switching element. In operation, while the switching element is programmed to a first resistive state, no current passes through the RSM element and while a second resistive state is programmed to the RSM element, current passes through the RSM element.
摘要翻译：一种非易失性存储单元及其使用方法。在一些实施例中，独立可编程电阻感测存储器（RSM）元件与可编程金属化单元（PMC）开关元件串联连接。在操作中，当开关元件被编程为第一电阻状态时，没有电流通过RSM元件，并且当第二电阻状态被编程到RSM元件时，电流通过RSM元件。

19. 发明申请

US20110007538A1 SYSTEMS AND METHODS OF CELL SELECTION IN CROSS-POINT ARRAY MEMORY DEVICES 有权
标题翻译：跨点阵列存储器件中的细胞选择的系统和方法
公开(公告)号：US20110007538A1
公开(公告)日：2011-01-13
申请号：US12502111
申请日：2009-07-13
申请人： Chulmin Jung , Jinyoung Kim , Yong Lu , Harry Liu
发明人： Chulmin Jung , Jinyoung Kim , Yong Lu , Harry Liu
IPC分类号： G11C5/02 , G11C7/00
CPC分类号： G11C13/0023 , G11C5/02 , G11C13/0038 , G11C2213/71
摘要： The disclosure is related to three dimensional cross-point array memory devices and selecting cells within a three dimensional cross-point array memory. In a particular embodiment, three different voltages levels are applied to bit lines of the cross point array to allow for selection of a specific cell. Series of select devices may be implemented to provide a high voltage and a low voltage to specific bit lines, while a middle voltage may also be provided. In a particular embodiment, the select devices comprise Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs).
摘要翻译：本公开涉及三维交叉点阵列存储器件并选择三维交叉点阵列存储器内的单元。在特定实施例中，将三个不同的电压电平施加到交叉点阵列的位线以允许选择特定单元。可以实现一系列选择装置以向特定位线提供高电压和低电压，同时还可以提供中间电压。在特定实施例中，选择器件包括金属氧化物半导体场效应晶体管（MOSFET）。

20. 发明授权

US07825478B2 Polarity dependent switch for resistive sense memory 有权
标题翻译：用于电阻式读出存储器的极性依赖开关
公开(公告)号：US07825478B2
公开(公告)日：2010-11-02
申请号：US12407823
申请日：2009-03-20
申请人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
发明人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
IPC分类号： H01L29/00 , H01L21/425
CPC分类号： G11C11/16 , G11C11/1659 , H01L27/228 , H01L29/1083
摘要： Polarity dependent switches for resistive sense memory are described. A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically connects to the bit contact. The source contact and the bit contact are asymmetrically implanted with dopant material.
摘要翻译：描述了用于电阻读出存储器的极性依赖开关。存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。半导体晶体管包括形成在基板上的栅极元件。半导体晶体管包括源极触点和位触点。门元件电连接源触点和触点触点。电阻式感测存储单元电连接到位触点。源极接触和位触点用掺杂剂材料非对称地注入。

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