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11. 发明授权

US06653026B2 Structure and method of correcting proximity effects in a tri-tone attenuated phase-shifting mask 有权
公开(公告)号：US06653026B2
公开(公告)日：2003-11-25
申请号：US09746369
申请日：2000-12-20
申请人： Christophe Pierrat , Youping Zhang
发明人： Christophe Pierrat , Youping Zhang
IPC分类号： G03F900
CPC分类号： G03F1/29 , G03F1/32 , G03F1/36
摘要： A structure and method are provided for correcting the optical proximity effects on a tri-tone attenuated phase-shifting mask. An attenuated rim, formed by an opaque region and an attenuated phase-shifting region, can be kept at a predetermined width across the mask or for certain types of structures. Typically, the attenuated rim is made as large as possible to maximize the effect of the attenuated phase-shifting region while still preventing the printing of larger portions of the attenuated phase-shifting region during the development process.

12. 发明授权

US06625801B1 Dissection of printed edges from a fabrication layout for correcting proximity effects 有权
公开(公告)号：US06625801B1
公开(公告)日：2003-09-23
申请号：US09676375
申请日：2000-09-29
申请人： Christophe Pierrat , Youping Zhang
发明人： Christophe Pierrat , Youping Zhang
IPC分类号： G06F1750
CPC分类号： G03F1/36 , Y10T428/24802
摘要： Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include correcting for proximity effects associated with an edge in a first fabrication layout by determining whether any portion of the edge corresponds to a target edge in a design layer. The first fabrication layout corresponds to the design layer that indicates target edges for a printed features layer. If any portion of the edge corresponds to the target edge, then it is determined whether to establish an evaluation point on the edge. Then it is determined how to correct the edge for proximity effects based on the evaluation point. In case it is determined that no portion of the edge corresponds to the target edge, then no evaluation point is selected on the edge.

13. 发明授权

US06453457B1 Selection of evaluation point locations based on proximity effects model amplitudes for correcting proximity effects in a fabrication layout 有权
标题翻译：基于邻近效应的评估点位置的选择用于在制造布局中校正邻近效应的模型幅度
公开(公告)号：US06453457B1
公开(公告)日：2002-09-17
申请号：US09676356
申请日：2000-09-29
申请人： Christophe Pierrat , Youping Zhang
发明人： Christophe Pierrat , Youping Zhang
IPC分类号： G06F1750
CPC分类号： G03F1/36 , G03F1/70 , Y10S977/734
摘要： Techniques for fabricating a device include forming a fabrication layout such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Included are techniques that correct for proximity effects associated with an edge in a layout corresponding to a design layer. An evaluation point is determined for the edge based on a profile of amplitudes output from a proximity effects model along a transect. The transect includes a target edge in the design layer corresponding to the edge. It is then determined how to correct at least a portion of the edge for proximity effects based on an analysis at the evaluation point. In other techniques, a dissection length parameter is derived based on a profile of amplitudes output by a proximity effects model along a transect. The transect includes a second edge in a second layout. An evaluation point is determined for a first edge based on the dissection length parameter. Then it is determined how to correct at least a portion of the first edge based on an analysis at the evaluation point.
摘要翻译：用于制造器件的技术包括形成用于物理设计层（例如集成电路的设计）的掩模布局的制造布局，以及识别与设计层对应的多边形的边缘上的评估点，用于校正邻近效应。包括的技术是校正与对应于设计层的布局中的边缘相关联的邻近效应。基于沿着截面的邻近效应模型输出的幅度分布，确定边缘的评估点。横断面包括对应于边缘的设计层中的目标边缘。然后基于评估点的分析确定如何校正边缘的至少一部分以用于邻近效应。在其他技术中，解剖长度参数是基于沿着截面的邻近效应模型输出的幅度分布导出的。横断面包括第二布局中的第二边缘。基于解剖长度参数确定第一边缘的评估点。然后，基于评估点的分析，确定如何校正第一边缘的至少一部分。

14. 发明授权

US07003757B2 Dissection of edges with projection points in a fabrication layout for correcting proximity effects 有权
标题翻译：在制造布局中用投影点解剖边缘以校正邻近效应
公开(公告)号：US07003757B2
公开(公告)日：2006-02-21
申请号：US10855673
申请日：2004-05-26
申请人： Christophe Pierrat , Youping Zhang
发明人： Christophe Pierrat , Youping Zhang
IPC分类号： G06F17/50 , G03C5/00
CPC分类号： G03F1/36 , G03F7/70441
摘要： Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include selecting from among all edges of all polygons in a proposed layout a subset of edges for which proximity corrections are desirable. The subset of edges includes less than all the edges. Evaluation points are established only for the subset of edges. Corrections are determined for at least portions of the subset of edges based on an analysis performed at the evaluation points. Other techniques include establishing a projection point on a first edge corresponding to the design layout based on whether a vertex of a second edge is within a halo distance. An evaluation point is determined for the first edge based on the projection point and characteristics of the first edge. It is then determined how to correct at least a portion of the edge for proximity effects based on an analysis at the evaluation point.
摘要翻译：用于制造器件的技术包括形成用于物理设计层（例如集成电路的设计）的制造布局，例如掩模布局，以及识别与设计层对应的多边形的边缘上的评估点，用于校正接近度效果。技术包括在所提出的布局中从所有多边形的所有边缘中选择需要接近校正的边缘子集。边缘子集包括少于所有边缘。仅针对边缘子集建立评估点。基于在评估点执行的分析，确定边缘子集的至少部分的校正。其他技术包括基于第二边缘的顶点是否在光晕距离内，在对应于设计布局的第一边缘上建立投影点。基于投影点和第一边缘的特性，确定第一边缘的评估点。然后基于评估点的分析确定如何校正边缘的至少一部分以用于邻近效应。

15. 发明授权

US06753115B2 Facilitating minimum spacing and/or width control optical proximity correction 有权
标题翻译：促进最小间距和/或宽度控制光学邻近校正
公开(公告)号：US06753115B2
公开(公告)日：2004-06-22
申请号：US10029041
申请日：2001-12-20
申请人： Youping Zhang , Christophe Pierrat
发明人： Youping Zhang , Christophe Pierrat
IPC分类号： G03F900
CPC分类号： G03F1/36
摘要： One embodiment of the invention provides a system that facilitates minimum spacing and/or width control during an optical proximity correction operation for a layout of a mask used in manufacturing an integrated circuit. During operation, the system considers a target edge of a first feature on the mask and then identifies a set of interacting edges in proximity to the target edge. Next, the system performs the optical proximity correction operation, wherein performing the optical proximity correction operation involves applying a first edge bias to the target edge to compensate for optical effects in a resulting image of the target edge. While applying the first edge bias to the target edge, the system allocates an available bias between the first edge bias for the target edge and a second edge bias for at least one edge in the set of interacting edges.
摘要翻译：本发明的一个实施例提供一种在用于制造集成电路的掩模的布局的光学邻近校正操作期间促进最小间隔和/或宽度控制的系统。在操作期间，系统考虑掩模上的第一特征的目标边缘，然后识别在目标边缘附近的一组交互边缘。接下来，系统执行光学邻近校正操作，其中执行光学邻近校正操作包括将第一边缘偏压施加到目标边缘以补偿目标边缘的所得图像中的光学效果。在将第一边缘偏压施加到目标边缘的同时，系统为目标边缘的第一边缘偏置和相互作用边缘集合中的至少一个边缘的第二边缘偏置分配可用偏置。

16. 发明授权

US06665856B1 Displacing edge segments on a fabrication layout based on proximity effects model amplitudes for correcting proximity effects 有权
标题翻译：基于用于校正邻近效应的邻近效应模型幅度，在制造布局上偏移边缘片段
公开(公告)号：US06665856B1
公开(公告)日：2003-12-16
申请号：US09728885
申请日：2000-12-01
申请人： Christophe Pierrat , Youping Zhang
发明人： Christophe Pierrat , Youping Zhang
IPC分类号： G06F1750
CPC分类号： G03F1/36 , G03F1/68 , G03F7/70441
摘要： Techniques for forming a fabrication layout, such as a mask, for a physical design layout, such as a layout for an integrated circuit, include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias.
摘要翻译：用于形成用于物理设计布局（例如集成电路的布局）的诸如掩模的制造布局的技术包括使用邻近效应模型来校正邻近效应的制造布局。执行邻近效应模型以产生初始输出。初始输出基于制造布局中的段的第一位置。第一位置从原始制造布局中的相应原始边缘移位等于初始偏置的距离。还执行该模型以基于该段的第二位置产生第二输出。第二位置从相应的原始边缘移位等于第二偏置的距离。基于初始输出和第二输出确定段的最佳偏差。基于最佳偏差，该段在制造布局中从相应的边缘移位。

17. 发明授权

US08281264B2 Model-based pattern characterization to generate rules for rule-model-based hybrid optical proximity correction 有权
标题翻译：基于模型的模式表征，以生成基于规则模型的混合光学邻近校正规则
公开(公告)号：US08281264B2
公开(公告)日：2012-10-02
申请号：US12592674
申请日：2009-12-01
申请人： Youping Zhang
发明人： Youping Zhang
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22
CPC分类号： G03F7/705 , G03F1/36 , G03F7/70441
摘要： A system and method are provided for analyzing layout patterns via simulation using a lithography model to characterize the patterns and generate rules to be used in rule-based optical proximity correction (OPC). The system and method analyze a series of layout patterns conforming to a set of design rules by simulation using a lithography model to obtain a partition of the pattern spaces into one portion that requires only rule-based OPC and another portion that requires model-based OPC. A corresponding hybrid OPC system and method are also introduced that utilize the generated rules to correct an integrated circuit (IC) design layout which reduces the OPC output complexity and improves turnaround time.
摘要翻译：提供了一种系统和方法，用于通过使用光刻模型的模拟来分析布局图案，以表征图案并生成将用于基于规则的光学邻近校正（OPC）中的规则。该系统和方法通过使用光刻模型进行模拟分析符合一组设计规则的一系列布局模式，以将模式空间的分区获得到仅需要基于规则的OPC的部分，并且需要基于模型的OPC的另一部分。还引入了一种相应的混合OPC系统和方法，利用生成的规则来校正集成电路（IC）设计布局，降低了OPC输出的复杂度并改善了周转时间。

18. 发明授权

US07585600B2 Method and apparatus for performing target-image-based optical proximity correction 有权
标题翻译：用于执行基于目标图像的光学邻近校正的方法和装置
公开(公告)号：US07585600B2
公开(公告)日：2009-09-08
申请号：US12112908
申请日：2008-04-30
申请人： Youping Zhang
发明人： Youping Zhang
IPC分类号： G03F9/00 , G06F17/50 , G06K9/00 , G03B27/42
CPC分类号： G03F9/00 , G03F1/30 , G03F1/36 , G03F1/70
摘要： A system that performs target-image-based optical proximity correction on masks that are used to generate an integrated circuit is presented. The system operates by first receiving a plurality of masks that are used to expose features on the integrated circuit. Next, the system computes a target image for a target feature defined by the plurality of masks, wherein mask features from different masks define the target image. The system dissects the feature into a plurality of segments, wherein dissecting the mask feature involves using dissection parameters associated with geometric characteristics of the target image, instead of using dissection parameters associated with geometric characteristics of the mask feature. The system then performs an optical proximity correction (OPC) operation on the plurality of masks, wherein the OPC operation uses parameters associated with geometric characteristics of the target image to perform optical proximity correction on the mask features that define the target image.
摘要翻译：提出了一种在用于生成集成电路的掩模上执行基于目标图像的光学邻近校正的系统。该系统首先接收用于暴露集成电路上的特征的多个掩模来操作。接下来，系统计算由多个掩模定义的目标特征的目标图像，其中来自不同掩模的掩模特征定义目标图像。该系统将特征解剖成多个段，其中解剖掩模特征涉及使用与目标图像的几何特征相关联的解剖参数，而不是使用与掩模特征的几何特征相关联的解剖参数。然后，系统对多个掩模执行光学邻近校正（OPC）操作，其中OPC操作使用与目标图像的几何特征相关联的参数来对限定目标图像的掩模特征进行光学邻近校正。

19. 发明申请

US20050223350A1 System for simplifying layout processing 有权
标题翻译：用于简化布局处理的系统
公开(公告)号：US20050223350A1
公开(公告)日：2005-10-06
申请号：US11091067
申请日：2005-03-28
申请人： Youping Zhang , Weinong Lai
发明人： Youping Zhang , Weinong Lai
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design by process biases, as well as design rule check and Boolean processes or process compensation.
摘要翻译：公开了用于集成电路设计的系统和方法，以通过应用布局处理来处理诸如集成电路设计布局中的点动的缺陷来增强电路布局的可制造性。布局处理可以应用于原始集成电路设计布局中的点动或通过过程偏差创建的后设计，以及设计规则检查和布尔过程或过程补偿。

20. 发明申请

US20050216875A1 System for integrated circuit layout partition and extraction for independent layout processing 有权
标题翻译：集成电路布局分区和提取系统，用于独立布局处理
公开(公告)号：US20050216875A1
公开(公告)日：2005-09-29
申请号：US11091305
申请日：2005-03-28
申请人： Youping Zhang , Weinong Lai
发明人： Youping Zhang , Weinong Lai
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/36
摘要： A system and method for integrated circuit design layout processing are disclosed to partition and extract the layout and optimize settings individually for an optimal solution to provide manufacturability enhancement. The integrated circuit design layout system and method are provided for splitting an integrated circuit layout into independent portions or pieces, which can be processed independently and reassembled together, based on prior information about the layout itself, or predefined data processing flow, which are commonly available at the time of processing individual layouts. The integrated circuit design layout system and method split the layout based on hierarchal geometry segregation rules that are derived from the layout data information or data processing flow.
摘要翻译：公开了一种用于集成电路设计布局处理的系统和方法，以分割和提取布局并单独优化设置以获得最佳解决方案以提供可制造性增强。提供集成电路设计布局系统和方法，用于将集成电路布局分为独立部分或片段，其可以基于关于布局本身或预定义的数据处理流程的先前信息被独立地和重新组装在一起，这是常用的在处理个人布局的时候。集成电路设计布局系统和方法基于从布局数据信息或数据处理流程导出的层次几何隔离规则分割布局。

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