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11. 发明授权

US07206223B1 MRAM memory with residual write field reset 失效
标题翻译： MRAM存储器具有残留写入域复位
公开(公告)号：US07206223B1
公开(公告)日：2007-04-17
申请号：US11297203
申请日：2005-12-07
申请人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Nicholas David Rizzo
发明人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Nicholas David Rizzo
IPC分类号： G11C11/00
CPC分类号： G11C11/15
摘要： A magnetoresistive random access memory (MRAM) (900) that is susceptible to a residual magnetic field is compensated during a write operation. A first magnetic field (208) is applied to a memory cell during a first time period, the first magnetic field having a first direction (y) and a first magnitude. A second magnetic field (212) is applied to the memory cell during a second time period and having a second direction (x) and a second magnitude. A third magnetic field (702) is applied to the memory cell during a third time period, wherein the third time period overlaps at least a portion of the second time period, the third magnetic field having a third direction (−y) which is approximately opposite to the first direction of the first magnetic field. Currents are selectively applied through conductors in the memory cell to apply the three magnetic fields.
摘要翻译：在写入操作期间补偿易受残余磁场影响的磁阻随机存取存储器（MRAM）（900）。第一磁场（208）在第一时间周期内被施加到存储单元，第一磁场具有第一方向（y）和第一大小。第二磁场（212）在第二时间段期间被施加到存储器单元并且具有第二方向（x）和第二大小。在第三时间段期间，第三磁场（702）被施加到存储器单元，其中第三时间周期与第二时间段的至少一部分重叠，第三磁场具有近似的第三方向（-y）与第一磁场的第一方向相反。通过存储单元中的导体选择性地施加电流以施加三个磁场。

12. 发明授权

US06903964B2 MRAM architecture with electrically isolated read and write circuitry 失效
标题翻译：具有电隔离读写电路的MRAM架构
公开(公告)号：US06903964B2
公开(公告)日：2005-06-07
申请号：US10185868
申请日：2002-06-28
申请人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Bradley J. Garni , Mark A. Durlam
发明人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Bradley J. Garni , Mark A. Durlam
IPC分类号： G11C11/16 , G11C11/00
CPC分类号： G11C11/16
摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.
摘要翻译：磁阻随机存取存储器（MRAM）具有单独的读写路径。这通过不需要在特定线路上的读取和写入功能之间切换来减少外围电路。通过具有专用于读取信号或写入信号的路径，可以针对这些功能优化电压电平。作为仅读取功能的一部分的选择晶体管可以是低电压型，因为它们不必接收写电路的相对较高的电压。类似地，写入电压不必降低以适应低电压型晶体管。整体存储器的大小保持有效小，同时提高性能。存储器单元被分组，使得与组相邻耦合到公共全局位线，这减少了为降低存储器单元选择提供电容减小组方法所需的空间。

13. 发明授权

US06711068B2 Balanced load memory and method of operation 有权
标题翻译：平衡负载记忆和操作方法
公开(公告)号：US06711068B2
公开(公告)日：2004-03-23
申请号：US10184720
申请日：2002-06-28
申请人： Chitra K. Subramanian , Brad J. Garni , Joseph J. Nahas , Halbert S. Lin , Thomas W. Andre
发明人： Chitra K. Subramanian , Brad J. Garni , Joseph J. Nahas , Halbert S. Lin , Thomas W. Andre
IPC分类号： G11C700
CPC分类号： G11C7/18 , G11C7/062 , G11C7/067 , G11C7/14 , G11C2207/005 , G11C2207/063
摘要： A memory provides a sensing scheme that maintains impedance balance between the route that the data takes to the sense amplifier and the route the reference or references take to the sense amplifier. Each sub-array of the memory has an adjacent column decoder that couples data to a data line that is also adjacent to the sub-array and may be considered part of the column decoder. The data for the selected sub-array is routed to the sense amplifier via its adjacent data line. The reference that is part of the selected sub-array is coupled to the data line of a non-selected sub-array. Thus the reference, which in the case of a MRAM type memory is preferably in close proximity to the location of the selected data, traverses a route to the sense amplifier that is impedance balanced with respect to the route taken by the data.
摘要翻译：存储器提供了一种感测方案，其保持数据到感测放大器的路由与参考或参考到读出放大器的路由之间的阻抗平衡。存储器的每个子阵列具有将数据耦合到也与子阵列相邻的数据线的相邻列解码器，并且可以被认为是列解码器的一部分。所选子阵列的数据通过其相邻数据线路由到读出放大器。作为所选子阵列的一部分的参考被耦合到未选择的子阵列的数据线。因此，在MRAM型存储器的情况下，参考优选地紧邻所选数据的位置，穿过相对于由数据采取的路由阻抗平衡的读出放大器的路线。

14. 发明授权

US06297095B1 Memory device that includes passivated nanoclusters and method for manufacture 有权
标题翻译：包含钝化纳米簇的记忆体装置及其制造方法
公开(公告)号：US06297095B1
公开(公告)日：2001-10-02
申请号：US09596399
申请日：2000-06-16
申请人： Ramachandran Muralidhar , Chitra K. Subramanian , Sucharita Madhukar , Bruce E. White , Michael A. Sadd , Sufi Zafar , David L. O'Meara , Bich-Yen Nguyen
发明人： Ramachandran Muralidhar , Chitra K. Subramanian , Sucharita Madhukar , Bruce E. White , Michael A. Sadd , Sufi Zafar , David L. O'Meara , Bich-Yen Nguyen
IPC分类号： H01L21336
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28273 , H01L29/66439 , H01L29/7888
摘要： A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). After growth of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). In order to prevent oxidation of the formed nanoclusters (21), the nanoclusters (21) may be encapsulated using various techniques prior to formation of the control dielectric layer (20). A gate electrode (24) is then formed over the control dielectric (20), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed. After formation of spacers (35), source and drain regions (32, 34) are then formed by implantation in the semiconductor layer (12) such that a channel region is formed between the source and drain regions (32, 34) underlying the gate electrode (24).
摘要翻译：提出了一种具有浮动栅极的半导体存储器件，其包括多个纳米团簇（21）和用于制造这种器件的技术。该器件通过首先提供其上形成有隧道介电层（14）的半导体衬底（12）形成。然后在隧道介电层（14）上生长多个纳米团簇（19）。在纳米团簇（21）生长之后，在纳米团簇（21）上形成控制电介质层（20）。为了防止形成的纳米团簇（21）的氧化，可以在形成控制电介质层（20）之前使用各种技术将纳米团簇（21）进行封装。然后在控制电介质（20）上形成栅极（24），并且选择性地去除不在栅电极下面的控制电介质，多个纳米团簇和栅极电介质的部分。在形成间隔物（35）之后，然后通过注入在半导体层（12）中形成源极和漏极区域（32,34），使得沟道区域形成在栅极下面的源极和漏极区域（32,34）之间电极（24）。

15. 发明授权

US07224630B2 Antifuse circuit 有权
标题翻译：防腐电路
公开(公告)号：US07224630B2
公开(公告)日：2007-05-29
申请号：US11166139
申请日：2005-06-24
申请人： Thomas W. Andre , Chitra K. Subramanian
发明人： Thomas W. Andre , Chitra K. Subramanian
IPC分类号： G11C7/02
CPC分类号： G11C17/18 , G11C11/1673 , G11C11/1695 , G11C11/5692 , G11C17/02
摘要： An antifuse circuit provides on a per bit basis a signal that indicates whether an MTJ (magnetic tunnel junction) antifuse has been previously programmed to a low resistance state in response to a program voltage. A sense amplifier provides the resistance state signal. A plurality of reference magnetic tunnel junctions are coupled in parallel and to the sense amplifier, each having a resistance within a range to provide a collective resistance that can be determined by the sense amplifier to differ from each resistance state of the MTJ antifuse. A write circuit selectively provides a current sufficient to create the program voltage when the write circuit is enabled to program the antifuse magnetic tunnel junction. Upon detecting a change in resistance in the MTJ antifuse, the write circuit reduces current supplied to the antifuse. Multiple antifuses may be programmed concurrently. Gate oxide thicknesses of transistors are adjusted for optimal performance.
摘要翻译：反熔丝电路以每比特为基础提供一个信号，该信号指示MTJ（磁性隧道结）反熔丝是否已经被预先编程为响应于编程电压的低电阻状态。读出放大器提供电阻状态信号。多个参考磁隧道结并联耦合到读出放大器，每个具有在一个范围内的电阻，以提供可由感测放大器确定的不同于MTJ反熔丝的每个电阻状态的集合电阻。写入电路选择性地提供足以在写入电路被编程反熔丝磁性隧道结时产生编程电压的电流。当检测到MTJ反熔丝中的电阻变化时，写入电路减少提供给反熔丝的电流。多个反熔丝可以同时编程。调整晶体管的栅极氧化物厚度以获得最佳性能。

16. 发明授权

US06859388B1 Circuit for write field disturbance cancellation in an MRAM and method of operation 失效
标题翻译： MRAM中的磁场干扰消除电路及其操作方法
公开(公告)号：US06859388B1
公开(公告)日：2005-02-22
申请号：US10656646
申请日：2003-09-05
申请人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian
发明人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian
IPC分类号： G11C11/14 , G11C11/00
CPC分类号： G11C11/14
摘要： A circuit and method for counteracting stray magnetic fields generated by write currents in an MRAM memory reuses the write current in adjoining write columns via a current redistribution bus at a first end of the write lines. A first switch connected to a second end of each write line controls the write current in the write line. If the first switch is not conductive, a second switch connects the second end of the write line to a reference voltage terminal. For write lines located at sub-array edges, a predetermined amount of spacing may be used to avoid magnetic field disturbance in an adjacent sub-array. The number of spaces required can be minimized by specific activation of write line switches.
摘要翻译：用于抵消由MRAM存储器中的写入电流产生的杂散磁场的电路和方法在写入线的第一端通过电流再分配总线重新使用相邻写入列中的写入电流。连接到每条写入线的第二端的第一开关控制写入线中的写入电流。如果第一开关不导通，则第二开关将写入线的第二端连接到参考电压端子。对于位于子阵列边缘的写入线，可以使用预定量的间隔来避免相邻子阵列中的磁场干扰。可以通过写入线开关的特定激活来最小化所需的空间数量。

17. 发明授权

US06842365B1 Write driver for a magnetoresistive memory 有权
标题翻译：为磁阻存储器写入驱动器
公开(公告)号：US06842365B1
公开(公告)日：2005-01-11
申请号：US10656676
申请日：2003-09-05
申请人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Halbert Lin
发明人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Halbert Lin
IPC分类号： G11C11/00 , G11C11/14 , G11C11/15 , G11C11/16
CPC分类号： G11C11/1695 , G11C11/1675
摘要： A write driver uses a reference current that is reflected to a driver circuit by a voltage. The driver circuit is sized in relation to the device that provides the voltage so that the current through the driver is a predetermined multiple of the reference current. This voltage is coupled to the driver circuit through a switch. The switch is controlled so that the driver circuit only receives the voltage when the write line is to have write current through it as determined by a decoder responsive to an address. The driver is affirmatively disabled when the write line is intended to not have current passing through it. As an enhancement to overcome ground bounce due to high currents, the input to the driver can be capacitively coupled to the ground terminal that experiences such bounce. Additional enhancements provide benefits in amplitude and edge rate control.
摘要翻译：写驱动器使用通过电压反映到驱动器电路的参考电流。驱动器电路的尺寸相对于提供电压的装置的尺寸，使得通过驱动器的电流是参考电流的预定倍数。该电压通过开关耦合到驱动电路。开关被控制，使得驱动电路仅在响应于地址由解码器确定的写入线要具有写入电流时才接收电压。当写行意图没有电流通过它时，驱动程序被肯定地禁用。作为克服由于高电流引起的地面反弹的增强，驱动器的输入可以电容耦合到经历这种反弹的接地端子。附加的增强功能可以提供幅度和边缘速率控制的优点。

18. 发明授权

US06738303B1 Technique for sensing the state of a magneto-resistive random access memory 有权
标题翻译：用于感测磁阻随机存取存储器的状态的技术
公开(公告)号：US06738303B1
公开(公告)日：2004-05-18
申请号：US10305736
申请日：2002-11-27
申请人： Chitra K. Subramanian , Bradley J. Garni
发明人： Chitra K. Subramanian , Bradley J. Garni
IPC分类号： G11C702
CPC分类号： G11C11/15
摘要： The state of a MRAM cell is detected when the magnetic tunnel junction (MTJ) of the MRAM cell has a reduced bias from the maximum voltage that is used for biasing. In one example, the MTJ of the selected cell and the MTJ of a reference cell are both biased to a first voltage. The MTJs then discharge this bias asymptotically (RC time constant based utilizing bit line capacitance and MTJ resistance) to a lower voltage such as ground but at rates that are different for the selected cell versus the reference cell due to MTJ resistance differential. At a predetermined time the voltage differential is detected. In another example, the MTJs are precharged to a low voltage then are driven asymptotically toward a higher voltage. Thus, at the time of sensing for both cases, the voltage across the MTJ is less than the bias voltage that is being used.
摘要翻译：当MRAM单元的磁隧道结（MTJ）具有从用于偏置的最大电压的偏差减小时，检测到MRAM单元的状态。在一个示例中，所选择的单元的MTJ和参考单元的MTJ均被偏置到第一电压。然后，MTJs渐近地将该偏置（基于利用位线电容和MTJ电阻的RC时间常数）放电到较低电压（例如接地），但是由于MTJ电阻差，对于所选择的单元与参考单元不同的速率。在预定时间，检测到电压差。在另一个例子中，MTJs被预充电到低电压，然后渐近地向更高的电压驱动。因此，在感测两种情况下，MTJ两端的电压小于所使用的偏置电压。

19. 发明授权

US06714440B2 Memory architecture with write circuitry and method therefor 有权
标题翻译：具有写入电路的存储器架构及其方法
公开(公告)号：US06714440B2
公开(公告)日：2004-03-30
申请号：US10185888
申请日：2002-06-28
申请人： Chitra K. Subramanian , Thomas W. Andre , Joseph J. Nahas
发明人： Chitra K. Subramanian , Thomas W. Andre , Joseph J. Nahas
IPC分类号： G11C1100
CPC分类号： G11C11/15
摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. Switchable current mirrors, each having multiple series-connected stages, receive a common reference current. A timing circuit provides control signals to word and bit decoders and to the switchable current mirrors to selectively complete current paths through a predetermined write word line and a predetermined write bit line. Bit lines are connected together at a common end, and word lines are connected together at a common end. By precharging a common rail having multiple write bit lines connected together, the write noise immunity is improved and current spikes are minimized. Groups of bit lines may be connected via a metal option to adjust a transition time of a programming current.
摘要翻译：磁阻随机存取存储器（MRAM）具有单独的读写路径。每个具有多个串联级的可切换电流镜接收公共参考电流。定时电路向字和位解码器和可切换电流镜提供控制信号，以选择性地完成通过预定写字线和预定写位线的电流路径。位线在公共端连接在一起，字线在公共端连接在一起。通过对连接在一起的多个写入位线的共轨进行预充电，改善了写入噪声抗扰度并使电流尖峰最小化。位线组可以通过金属选项来连接，以调整编程电流的转换时间。

20. 发明授权

US06621729B1 Sense amplifier incorporating a symmetric midpoint reference 有权
标题翻译：包含对称中点参考的感应放大器
公开(公告)号：US06621729B1
公开(公告)日：2003-09-16
申请号：US10185224
申请日：2002-06-28
申请人： Bradley J. Garni , Chitra K. Subramanian , Joseph J. Nahas , Thomas W. Andre
发明人： Bradley J. Garni , Chitra K. Subramanian , Joseph J. Nahas , Thomas W. Andre
IPC分类号： G11C1100
CPC分类号： G11C11/14 , G11C7/062 , G11C7/067 , G11C2207/063
摘要： A sense amplifier (10) develops internally a midpoint reference current from two reference bits. The midpoint reference current is used to sense the state of a memory bit having at least two distinct resistance states (H and L) by determining whether the sense memory bit develops a larger or smaller current. The midpoint reference current is developed within a single sense amplifier. Predetermined bias voltages are developed from each of a data bit cell, a reference cell programmed to a high state and a reference cell programmed to a low state. Currents are developed from the bias voltages and summed to create the midpoint reference current. A current differential amplifier senses whether the bit input has a high or low resistive state and outputs a voltage indicative of the sensed memory state.
摘要翻译：读出放大器（10）内部产生来自两个参考位的中点参考电流。中点参考电流用于通过确定感测存储器位是否产生较大或更小的电流来感测具有至少两个不同电阻状态（H和L）的存储器位的状态。在单个读出放大器内开发中点参考电流。从数据位单元，被编程为高状态的参考单元和被编程为低状态的参考单元中的每一个产生预定的偏置电压。电流从偏置电压开始，并相加以产生中点参考电流。电流差分放大器感测位输入是否具有高电阻状态或低电阻状态，并且输出指示感测到的存储器状态的电压。

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