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11. 发明授权

US5202593A Bi-directional bus repeater 失效
标题翻译：双向总线中继器
公开(公告)号：US5202593A
公开(公告)日：1993-04-13
申请号：US785299
申请日：1991-10-30
申请人： Thomas B. Huang , Yih-Chyun Jenq , Keith Lofstrom
发明人： Thomas B. Huang , Yih-Chyun Jenq , Keith Lofstrom
IPC分类号： H03K19/0175 , H03K5/02 , H04L5/16
CPC分类号： H03K5/026
摘要： A bi-directional bus repeater includes two unidirectional bus repeaters connected for retransmitting signals in opposite directions between two buses. When an external bus driver pulls either bus low, one of the unidirectional bus repeaters pulls the other bus low. When the external bus driver allows the bus to rise to the high logic level, the unidirectional bus repeater temporarily supplies a high charging current to the other bus to quickly pull it up. Each unidirectional bus repeater also generates signals indicating when it is actively pulling its output bus up or down and the indicating signals inhibit one unidirectional bus repeater from actively driving its output when the other unidirectional bus repeater is actively driving its output.
摘要翻译：双向总线中继器包括两个单向总线中继器，用于在两条总线之间的相反方向重新发送信号。当外部总线驱动器将总线拉低时，其中一个单向总线中继器将另一个总线拉低。当外部总线驱动器允许总线上升到高逻辑电平时，单向总线中继器临时向另一个总线提供高充电电流，以快速将其拉高。每个单向总线中继器还产生指示何时正在向上或向下拉动其输出总线的信号，并且当另一个单向总线中继器正在主动驱动其输出时，指示信号禁止一个单向总线中继器主动驱动其输出。

12. 发明授权

US07353162B2 Scalable reconfigurable prototyping system and method 有权
标题翻译：可扩展可重构原型系统和方法
公开(公告)号：US07353162B2
公开(公告)日：2008-04-01
申请号：US11056961
申请日：2005-02-11
申请人： Thomas B. Huang , Mon-Ren Chene
发明人： Thomas B. Huang , Mon-Ren Chene
IPC分类号： G06F9/455
CPC分类号： G06F17/5027
摘要： A method and a system provide a reconfigurable platform for designing and emulating a user design. The method and system facilitates design and emulation of a system-on-a-chip type user design. The netlist of a user design may be included with netlists from customized or optimized third party circuits in an emulation using a platform including a number of field programmable devices. Various customized circuits for specific development activities, such as debugging, performance analysis, and simulator linkage may be configured to interact with the user design.
摘要翻译：一种方法和系统提供了一种用于设计和仿真用户设计的可重构平台。该方法和系统促进了片上系统类型用户设计的设计和仿真。使用包括多个现场可编程设备的平台在仿真中可以使用来自定制或优化的第三方电路的网表列出用户设计的网表。用于特定开发活动的各种定制电路，例如调试，性能分析和模拟器连接可以被配置为与用户设计交互。

13. 发明授权

US5940603A Method and apparatus for emulating multi-ported memory circuits 失效
标题翻译：用于仿真多端口存储器电路的方法和装置
公开(公告)号：US5940603A
公开(公告)日：1999-08-17
申请号：US953315
申请日：1997-10-17
申请人： Thomas B. Huang
发明人： Thomas B. Huang
IPC分类号： G06F11/22 , G06F17/50 , G11C7/00 , G11C8/16 , G06F3/00
CPC分类号： G11C7/00 , G06F11/22 , G06F17/5027 , G11C8/16
摘要： A memory design is implemented in static memory circuits having a plurality of bidirectional access ports, wherein each port is configured for read or write access. The memory design defines initial contents, depth, width, and bank selection in the memory circuits according to predefined configuration values, as well as, for each access port, whether that access port is configured for read or write. Port access occurs during time slots, which are based on external clock signals and memory circuit access times. Modified memory designs may be implemented such that access ports are accordingly reconfigured.
摘要翻译：在具有多个双向访问端口的静态存储器电路中实现存储器设计，其中每个端口被配置用于读取或写入访问。存储器设计根据预定义的配置值定义存储器电路中的初始内容，深度，宽度和存储体选择，以及针对每个访问端口，该访问端口是否配置为读取或写入。端口访问发生在基于外部时钟信号和存储器电路访问时间的时隙期间。可以实现改进的存储器设计，使得相应地重新配置接入端口。

14. 发明授权

US5835751A Structure and method for providing reconfigurable emulation circuit 失效
标题翻译：提供可重构仿真电路的结构和方法
公开(公告)号：US5835751A
公开(公告)日：1998-11-10
申请号：US893412
申请日：1997-07-11
申请人： Nang-Ping Chen , Robert J. Ko , Jeong-Tyng Li , Thomas B. Huang , Ming-Yang Wang
发明人： Nang-Ping Chen , Robert J. Ko , Jeong-Tyng Li , Thomas B. Huang , Ming-Yang Wang
IPC分类号： G06F1/10 , A21B1/24 , F24C15/32 , G06F1/12 , G06F11/26 , G06F17/50 , H01L21/82 , H03K19/177 , G06F9/44
CPC分类号： A21B1/245 , G06F17/5027 , G06F17/5054
摘要： A method and a structure provide emulation circuit implemented on a logic block module comprising clocked and unclocked field programmable logic devices (FPGAs). Software modules analyze the target logic circuit and impose delay constraints to require certain storage instances to be implemented on separate FPGAs so as to prevent hold time violation artifacts.
摘要翻译：一种方法和结构提供了在包括时钟和未锁定的现场可编程逻辑器件（FPGA）的逻辑块模块上实现的仿真电路。软件模块分析目标逻辑电路并施加延迟约束，要求在单独的FPGA上实现某些存储实例，以防止保持时间违规伪像。

15. 发明授权

US5563829A Multi-port memory emulation using tag registers 失效
公开(公告)号：US5563829A
公开(公告)日：1996-10-08
申请号：US522865
申请日：1995-09-01
申请人： Thomas B. Huang
发明人： Thomas B. Huang
IPC分类号： G11C11/401 , G06F17/50 , G11C8/16 , G11C13/00
CPC分类号： G06F17/5027 , G11C8/16
摘要： A method of implementing a multi-port memory circuit in the memory resources of configuration logic blocks of programmable logic devices. The multi-port memory circuit to be implemented comprises a memory array having memory locations for storing data, read ports for reading data from the memory array and write ports for writing data to the memory array. Multiple duplications of the memory array are created in order to implement as many read ports and write ports as the multi-port memory circuit being implemented. The memory locations within the duplicate memory arrays are tagged to indicate which memory location had data written therein last so that only the last written data will be read through the various read ports.

16. 发明授权

US5448522A Multi-port memory emulation using tag registers 失效
标题翻译：使用标签寄存器进行多端口存储器仿真
公开(公告)号：US5448522A
公开(公告)日：1995-09-05
申请号：US217049
申请日：1994-03-24
申请人： Thomas B. Huang
发明人： Thomas B. Huang
IPC分类号： G11C11/401 , G06F17/50 , G11C8/16 , G11C13/00
CPC分类号： G06F17/5027 , G11C8/16
摘要： A method of implementing a multi-port memory circuit in the memory resources of configuration logic blocks of programmable logic devices. The multi-port memory circuit to be implemented comprises a memory array having memory locations for storing data, read ports for reading data from the memory array and write ports for writing data to the memory array. Multiple duplications of the memory array are created in order to implement as many read ports and write ports as the multi-port memory circuit being implemented. The memory locations within the duplicate memory arrays are tagged to indicate which memory location had data written therein last so that only the last written data will be read through the various read ports.
摘要翻译：一种在可编程逻辑器件的配置逻辑块的存储器资源中实现多端口存储器电路的方法。要实现的多端口存储器电路包括具有用于存储数据的存储器位置的存储器阵列，用于从存储器阵列读取数据的读取端口和用于将数据写入存储器阵列的写入端口。创建存储器阵列的多个重复以便实现与实现的多端口存储器电路一样多的读取端口和写入端口。重复存储器阵列中的存储器位置被标记以指示哪个存储器位置具有最后写入的数据，使得只有最后写入的数据将通过各种读取端口读取。

17. 发明授权

US5425036A Method and apparatus for debugging reconfigurable emulation systems 失效
标题翻译：用于调试可重构仿真系统的方法和装置
公开(公告)号：US5425036A
公开(公告)日：1995-06-13
申请号：US947308
申请日：1992-09-18
申请人： Dick L. Liu , Jeong-Tyng Li , Thomas B. Huang , Kenneth S. K. Choi
发明人： Dick L. Liu , Jeong-Tyng Li , Thomas B. Huang , Kenneth S. K. Choi
IPC分类号： G06F17/50 , G06F15/60
CPC分类号： G06F17/5027
摘要： An improved electronic design automation (EDA) system employs field programmable gate arrays (FPGAs) for emulating prototype circuit designs. A circuit netlist file is down-loaded to the FPGAs to configure the FPGAs to emulate a functional representation of the prototype circuit. To check whether the circuit netlist is implemented properly, the FPGAs are tested functionally by applying input vectors thereto and comparing the resulting output of the FPGAs to output vectors provided from prior simulation. If the FPGAs fail such vector comparison, the FPGAs are debugged by inserting "read-back" trigger instructions in the input vectors, preferably corresponding to fail points in the applied vector stream. Modifying the input vectors with such read-back signals causes the internal states of latches and flip-flops in each FPGA to be captured when functional testing is repeated. Such internal state information is useful for debugging the FPGAs, and particularly convenient because no recompilation of the circuit netlist is required. A similar approach which also uses the read-back feature of FPGAs is employed to debug FPGAs coupled to a target system which appears to fail during emulation runs.
摘要翻译：改进的电子设计自动化（EDA）系统采用现场可编程门阵列（FPGA）来仿真原型电路设计。电路网表文件被下载到FPGA，以配置FPGA模拟原型电路的功能表示。为了检查电路网表是否正确地实现，通过向其施加输入向量并且将所得到的FPGA的输出与从先前的仿真提供的输出向量进行比较来功能地测试FPGA。如果FPGA不通过这样的矢量比较，则通过在输入向量中插入“回读”触发指令来调试FPGA，优选地对应于所应用的矢量流中的故障点。使用这种读回信号修改输入向量会导致在重复功能测试时捕获每个FPGA中的锁存器和触发器的内部状态。这种内部状态信息对调试FPGA非常有用，特别方便，因为不需要重新编译电路网表。采用FPGA使用回读特性的类似方法可用于调试耦合到目标系统的FPGA，仿真运行期间似乎失败。

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