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11. 发明申请

US20070102754A1 NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20070102754A1
公开(公告)日：2007-05-10
申请号：US11163984
申请日：2005-11-07
申请人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A single-poly non-volatile memory device invented to integrate into logic process is disclosed. This non-volatile memory device includes a memory cell unit comprising a PMOS access transistor that is serially connected to a PMOS storage transistor formed in a cell array area, and, in a peripheral circuit area, a high-voltage MOS transistor having a high-voltage gate insulation layer is provided. The PMOS access transistor has an access gate oxide layer that has a thickness equal to the thickness of the high-voltage gate insulation layer in a peripheral circuit area.
摘要翻译：公开了发明用于集成到逻辑过程中的单一多重非易失性存储器件。该非易失性存储器件包括存储单元单元，该存储单元单元包括串联连接到形成在单元阵列区域中的PMOS存储晶体管的PMOS存取晶体管，在外围电路区域中，具有高电压MOS晶体管，提供了电压栅极绝缘层。 PMOS存取晶体管具有与外围电路区域中的高压栅极绝缘层的厚度相等的栅极氧化层。

12. 发明授权

US07190623B2 Non-volatile memory cell and method of operating the same 有权
标题翻译：非易失性存储单元及其操作方法
公开(公告)号：US07190623B2
公开(公告)日：2007-03-13
申请号：US11161951
申请日：2005-08-23
申请人： Ching-Hsiang Hsu , Shih-Jye Shen , Hsin-Ming Chen , Hai-Ming Lee
发明人： Ching-Hsiang Hsu , Shih-Jye Shen , Hsin-Ming Chen , Hai-Ming Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A memory cell includes an N-type well, three P-type doped regions formed on the N-type well, a dielectric layer formed on the N-type well and between a first doped region and a second doped region of the three P-type doped regions, a first gate formed on the dielectric layer, a charge storage structure formed on the N-type well and between the second doped region and a third doped region of the three P-type doped regions, and a second gate formed on the charge storage structure. Data is stored in the memory cell by injecting electrons based on the channel-hot-hole induced hot-electron injection mechanism, the band-to-band tunneling induced electron injection mechanism and the Fowler-Nordheim tunneling mechanism. Data is erased from the memory cell by ejecting electrons based on the Fowler-Nordheim tunneling mechanism. Whether data is stored in the charge storage structure or not can be distinguished by read operation.
摘要翻译：存储单元包括N型阱，形成在N型阱上的三个P型掺杂区，形成在N型阱上的介质层，以及在三个P型掺杂区的第三掺杂区和第三掺杂区之间，形成在电介质层上的第一栅极，形成在N型阱上的电荷存储结构，以及形成在三个P型掺杂区域的第二掺杂区域和第三掺杂区域之间的电荷存储结构，电荷存储结构。基于通道 - 热孔感应的热电子注入机制，带 - 带隧道诱导电子注入机制和Fowler-Nordheim隧道机制，通过注入电子将数据存储在存储单元中。基于Fowler-Nordheim隧道机制，通过弹出电子从存储器单元擦除数据。数据是否存储在电荷存储结构中是否可以通过读取操作进行区分。

13. 发明申请

US20050179095A1 NON-VOLATILE MEMORY CELL 审中-公开
标题翻译：非挥发性记忆细胞
公开(公告)号：US20050179095A1
公开(公告)日：2005-08-18
申请号：US10908114
申请日：2005-04-28
申请人： Ching-Hsiang Hsu , Shih-Jye Shen , Hsin-Ming Chen , Hai-Ming Lee
发明人： Ching-Hsiang Hsu , Shih-Jye Shen , Hsin-Ming Chen , Hai-Ming Lee
IPC分类号： G11C16/04 , G11C16/10 , H01L21/8246 , H01L27/115 , H01L29/76 , H01L29/792
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/10 , H01L27/115 , H01L29/7923
摘要： A memory cell is disclosed. The memory cell includes an N-well, three P-type doped regions formed on the N-type well, a first stacked dielectric layer formed on the N-type well and between a first doped region and a second doped region from among the three P-type doped regions, a first gate formed on the first stacked dielectric layer, a second stacked dielectric layer formed on the N-type well and between the second doped region and a third doped region from among the three P-type doped regions, and a second gate formed on the second stacked dielectric layer.
摘要翻译：公开了一种存储器单元。存储单元包括N阱，形成在N型阱上的三个P型掺杂区，形成在N型阱上的第一层叠电介质层，以及在三层阱中的第一掺杂区和第二掺杂区之间 P型掺杂区域，形成在第一堆叠介质层上的第一栅极，形成在N型阱上的第二堆叠电介质层，以及在三个P型掺杂区域中的第二掺杂区域和第三掺杂区域之间，以及形成在所述第二堆叠电介质层上的第二栅极。

14. 发明申请

US20050145927A1 NON-VOLATILE MEMORY CELL 有权
公开(公告)号：US20050145927A1
公开(公告)日：2005-07-07
申请号：US10905056
申请日：2004-12-13
申请人： Ching-Hsiang Hsu , Shih-Jye Shen , Hsin-Ming Chen , Hai-Ming Lee
发明人： Ching-Hsiang Hsu , Shih-Jye Shen , Hsin-Ming Chen , Hai-Ming Lee
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/76
CPC分类号： G11C16/0433 , G11C16/0466 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/7923
摘要： A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well and between the first doped region and the second doped region from among the three P-type doped regions. The first gate is formed on the first stacked dielectric layer. The second stacked dielectric layer is formed on the N-type well and between the second doped region and the third doped region from among the three P-type doped regions. The second gate is formed on the second stacked dielectric layer.

15. 发明授权

US07960792B2 Non-volatile memory with a stable threshold voltage on SOI substrate 有权
标题翻译：在SOI衬底上具有稳定阈值电压的非易失性存储器
公开(公告)号：US07960792B2
公开(公告)日：2011-06-14
申请号：US12943945
申请日：2010-11-11
申请人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： H01L29/786 , H01L29/792
CPC分类号： H01L27/115
摘要： A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.
摘要翻译：设置在SOI衬底中的非易失性存储器。非易失性存储器包括存储单元和第一导电类型掺杂区域。存储单元包括栅极，电荷存储结构，底部电介质层，第二导电类型漏极区域和第二导电型源极区域。栅极设置在SOI衬底上。电荷存储结构设置在栅极和SOI衬底之间。底部电介质层设置在电荷存储层和SOI衬底之间。第二导电型漏极区域和第二导电型源极区域设置在栅极的两侧旁边的第一导电型硅体层中。第一导电型掺杂区域设置在第一导电型硅体层中，并且与栅极下方的第一导电型硅体层电连接。

16. 发明授权

US07682908B2 Non-volatile memory and operating method thereof 有权
标题翻译：非易失性存储器及其操作方法
公开(公告)号：US07682908B2
公开(公告)日：2010-03-23
申请号：US11163716
申请日：2005-10-28
申请人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： H01L21/336 , H01L27/088 , H01L27/108
CPC分类号： H01L29/792 , G11C16/0433 , G11C16/10 , H01L27/115
摘要： A non-volatile memory including a substrate, a first doped region, a second doped region, a third doped region, a first gate structure, and a second gate structure is disclosed. The doped regions are disposed in the substrate and the second doped region is disposed between the first doped region and the third doped region. The first gate structure is disposed on the substrate between the first doped region and the second doped region. The second gate structure is disposed on the substrate between the second doped region and the third doped region, and comprises a tunneling dielectric layer, a charge trapping structure and a gate from the bottom up.
摘要翻译：公开了包括衬底，第一掺杂区，第二掺杂区，第三掺杂区，第一栅极结构和第二栅极结构的非易失性存储器。掺杂区域设置在衬底中，第二掺杂区域设置在第一掺杂区域和第三掺杂区域之间。第一栅极结构设置在第一掺杂区和第二掺杂区之间的衬底上。第二栅极结构设置在第二掺杂区域和第三掺杂区域之间的衬底上，并且包括隧道电介质层，电荷捕获结构和从下向上的栅极。

17. 发明授权

US07250654B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US07250654B2
公开(公告)日：2007-07-31
申请号：US11163984
申请日：2005-11-07
申请人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A single-poly non-volatile memory device invented to integrate into logic process is disclosed. This non-volatile memory device includes a memory cell unit comprising a PMOS access transistor that is serially connected to a PMOS storage transistor formed in a cell array area, and, in a peripheral circuit area, a high-voltage MOS transistor having a high-voltage gate insulation layer is provided. The PMOS access transistor has an access gate oxide layer that has a thickness equal to the thickness of the high-voltage gate insulation layer in a peripheral circuit area.
摘要翻译：公开了发明用于集成到逻辑过程中的单一多重非易失性存储器件。该非易失性存储器件包括存储单元单元，该存储单元单元包括串联连接到形成在单元阵列区域中的PMOS存储晶体管的PMOS存取晶体管，并且在外围电路区域中具有高电压MOS晶体管，提供了电压栅极绝缘层。 PMOS存取晶体管具有与外围电路区域中的高压栅极绝缘层的厚度相等的栅极氧化层。

18. 发明授权

US07172940B1 Method of fabricating an embedded non-volatile memory device 有权
标题翻译：制造嵌入式非易失性存储器件的方法
公开(公告)号：US07172940B1
公开(公告)日：2007-02-06
申请号：US11162572
申请日：2005-09-15
申请人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Hsin-Ming Chen , Hai-Ming Lee , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： H01L21/8247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573 , H01L29/66833 , Y10S438/954
摘要： A method of fabricating a non-volatile memory based on SONOS is disclosed. By masking the peripheral circuit area with a reverse ONO photoresist layer, the residual ONO layer that is not covered by a gate within the memory array area is etched away to expose the substrate. After the etching of the ONO layer, a channel adjustment doping is carried out subsequently using the reverse ONO photoresist layer as an implant mask, thereby forming lightly doped regions next to the gate within the memory array area. Finally, the reverse ONO photoresist layer is then stripped.
摘要翻译：公开了一种制造基于SONOS的非易失性存储器的方法。通过用反向ONO光致抗蚀剂层掩蔽外围电路区域，蚀刻掉未被存储器阵列区域内的栅极覆盖的残余ONO层以露出衬底。在ONO层的蚀刻之后，随后使用反向ONO光致抗蚀剂层作为注入掩模进行沟道调节掺杂，从而在存储器阵列区域内形成栅极旁边的轻掺杂区域。最后，剥离反向ONO光致抗蚀剂层。

19. 发明申请

US20050282332A1 NON-VOLATILE MEMORY CELL AND METHOD OF OPERATING THE SAME 有权
标题翻译：非挥发性记忆体及其操作方法
公开(公告)号：US20050282332A1
公开(公告)日：2005-12-22
申请号：US11161951
申请日：2005-08-23
申请人： Ching-Hsiang Hsu , Shih-Jye Shen , Hsin-Ming Chen , Hai-Ming Lee
发明人： Ching-Hsiang Hsu , Shih-Jye Shen , Hsin-Ming Chen , Hai-Ming Lee
IPC分类号： G11C11/34 , G11C16/04 , G11C16/10 , H01L21/336 , H01L21/8238 , H01L21/8246 , H01L27/108 , H01L27/115 , H01L29/76 , H01L29/792 , H01L29/94 , H01L31/119
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A memory cell includes an N-type well, three P-type doped regions formed on the N-type well, a dielectric layer formed on the N-type well and between a first doped region and a second doped region of the three P-type doped regions, a first gate formed on the dielectric layer, a charge storage structure formed on the N-type well and between the second doped region and a third doped region of the three P-type doped regions, and a second gate formed on the charge storage structure. Data is stored in the memory cell by injecting electrons based on the channel-hot-hole induced hot-electron injection mechanism, the band-to-band tunneling induced electron injection mechanism and the Fowler-Nordheim tunneling mechanism. Data is erased from the memory cell by ejecting electrons based on the Fowler-Nordheim tunneling mechanism. Whether data is stored in the charge storage structure or not can be distinguished by read operation.
摘要翻译：存储单元包括N型阱，形成在N型阱上的三个P型掺杂区，形成在N型阱上的介质层，以及在三个P型掺杂区的第三掺杂区和第三掺杂区之间，形成在电介质层上的第一栅极，形成在N型阱上的电荷存储结构，以及形成在三个P型掺杂区域的第二掺杂区域和第三掺杂区域之间的电荷存储结构，电荷存储结构。基于通道 - 热孔感应的热电子注入机制，带 - 带隧道诱导电子注入机制和Fowler-Nordheim隧道机制，通过注入电子将数据存储在存储单元中。基于Fowler-Nordheim隧道机制，通过弹出电子从存储器单元擦除数据。数据是否存储在电荷存储结构中是否可以通过读取操作进行区分。

20. 发明授权

US06975545B2 Non-volatile memory cell 有权
标题翻译：非易失性存储单元
公开(公告)号：US06975545B2
公开(公告)日：2005-12-13
申请号：US10707700
申请日：2004-01-05
申请人： Ching-Hsiang Hsu , Shih-Jye Shen , Hsin-Ming Chen , Hai-Ming Lee
发明人： Ching-Hsiang Hsu , Shih-Jye Shen , Hsin-Ming Chen , Hai-Ming Lee
IPC分类号： G11C16/04 , G11C16/10 , H01L21/8246 , H01L27/115 , H01L29/76 , H01L29/792
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/10 , H01L27/115 , H01L29/7923
摘要： A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well and between the first doped region and the second doped region from among the three P-type doped regions. The first gate is formed on the first stacked dielectric layer. The second stacked dielectric layer is formed on the N-type well and between the second doped region and the third doped region from among the three P-type doped regions. The second gate is formed on the second stacked dielectric layer.
摘要翻译：存储单元包括N型阱，三个P型掺杂区，第一层叠电介质层，第一栅极，第二堆叠电介质层和第二栅极。在N阱上形成三个P型掺杂区域。在三个P型掺杂区域中，第一电介质叠层形成在N型阱上，并且在第一掺杂区和第二掺杂区之间。第一栅极形成在第一堆叠电介质层上。在三个P型掺杂区域中，第二层叠电介质层形成在N型阱上，并且在第二掺杂区域和第三掺杂区域之间。第二栅极形成在第二堆叠电介质层上。

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