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11. 发明授权

US07941612B2 Multipath accessible semiconductor memory device with host interface between processors 有权
标题翻译：多路径可访问的半导体存储器件，具有处理器之间的主机接口
公开(公告)号：US07941612B2
公开(公告)日：2011-05-10
申请号：US11829859
申请日：2007-07-27
申请人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Dong-Hyuk Lee , Jong-Wook Park , Ho-Cheol Lee , Mi-Jo Kim , Jung-Sik Kim , Chang-Ho Lee
发明人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Dong-Hyuk Lee , Jong-Wook Park , Ho-Cheol Lee , Mi-Jo Kim , Jung-Sik Kim , Chang-Ho Lee
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G11C7/1012 , G11C11/4096
摘要： A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.
摘要翻译：多路可及半导体存储器件提供处理器之间的接口功能。存储器设备可以包括具有可操作地耦合到两个或更多个端口的共享存储器区域的存储单元阵列，该两个或多个端口可由两个或多个处理器独立地访问;访问路径形成单元，用于在一个端口和共享之间形成数据访问路径响应于由处理器施加的外部信号的存储区域以及具有信号量区域和由两个或多个处理器在共享存储器区域中可访问的邮箱区域的接口单元，以提供用于两个或多个处理器之间的通信的接口功能。

12. 发明授权

US08473694B2 Memory device and memory system comprising same 有权
标题翻译：包含其的存储器件和存储器系统
公开(公告)号：US08473694B2
公开(公告)日：2013-06-25
申请号：US12885728
申请日：2010-09-20
申请人： Dong-Hyuk Lee , Jung-Bae Lee , Ki-Won Park
发明人： Dong-Hyuk Lee , Jung-Bae Lee , Ki-Won Park
IPC分类号： G06F12/00
CPC分类号： G11C29/08 , G11C11/401
摘要： A memory device comprises a memory cell array comprising a plurality of memory blocks each comprising a plurality of memory cells and a control setting circuit. The control setting circuit divides the memory blocks into at least first and second groups based on whether each of the memory blocks comprises at least one substandard memory cell, and sets individually control parameters of the first and second groups. The substandard memory cells are identified based on test results of the memory cells with respect to at least one of the control parameters. Each memory block in the first group comprises at least one substandard memory cell, and each memory block in the second group comprises no substandard memory cell.
摘要翻译：存储器装置包括存储单元阵列，其包括多个存储块，每个存储块包括多个存储单元和控制设置电路。控制设置电路基于每个存储器块是否包括至少一个不合标准的存储器单元，将存储器块分成至少第一组和第二组，并且分别设置第一组和第二组的控制参数。基于存储器单元相对于至少一个控制参数的测试结果来识别不合格存储器单元。第一组中的每个存储器块包括至少一个不合标准存储器单元，并且第二组中的每个存储器块都不包括不合格存储器单元。

13. 发明授权

US07870326B2 Multiprocessor system and method thereof 有权
标题翻译：多处理器系统及其方法
公开(公告)号：US07870326B2
公开(公告)日：2011-01-11
申请号：US11819601
申请日：2007-06-28
申请人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
发明人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
IPC分类号： G06F12/00
CPC分类号： G06F12/02
摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.
摘要翻译：提供了一种多处理器系统及其方法。示例性多处理器系统可以包括第一和第二处理器，具有存储单元阵列的动态随机存取存储器，所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组，耦合到第二存储器组的第二存储器组和第四存储器组处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组，以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元，如同样的通过第一和第二端口的存储器地址，使得第一和第二存储器组的起始地址在引导中变得相等，并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址，通过第二个端口，银行地址选择第四个存储器，作为与银行地址相同的银行地址，选择第三个存储器银行通过第一个港口。

14. 发明申请

US20110107006A1 Multiprocessor system and method thereof 审中-公开
公开(公告)号：US20110107006A1
公开(公告)日：2011-05-05
申请号：US12929222
申请日：2011-01-10
申请人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
发明人： Yun-Hee Shin , Han-Gu Sohn , Young-Min Lee , Ho-Cheol Lee , Soo-Young Kim , Dong-Hyuk Lee , Chang-Ho Lee
IPC分类号： G06F12/00
CPC分类号： G06F12/02
摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

15. 发明授权

US08520461B2 Row address code selection based on locations of substandard memory cells 有权
标题翻译：基于不合格存储单元位置的行地址码选择
公开(公告)号：US08520461B2
公开(公告)日：2013-08-27
申请号：US12832208
申请日：2010-07-08
申请人： Dong-Hyuk Lee , Jung-Bae Lee , Ki-Won Park
发明人： Dong-Hyuk Lee , Jung-Bae Lee , Ki-Won Park
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40618 , G11C11/40622 , G11C17/16 , G11C2211/4061
摘要： A memory device identifies memory blocks that contain substandard memory cells. The memory device then determines row address codes to apply to the memory blocks during refresh operations. The row address codes determine which memory blocks of the memory block are refreshed together. The row address codes are designed to ensure that memory blocks having substandard memory cells, which must be refreshed more frequently than other cells, are refreshed together, while memory blocks without substandard memory cells are refreshed together.
摘要翻译：存储器设备识别包含不合标准存储器单元的存储器块。然后，存储器件在刷新操作期间确定应用于存储器块的行地址代码。行地址代码确定存储器块的哪些存储器块被一起刷新。行地址码被设计为确保具有不同于其它单元的频率更新的不合格存储器单元的存储器块被一起刷新，而没有不合格存储器单元的存储器块被刷新在一起。

16. 发明授权

US08208335B2 Semiconductor memory device and system including the same 有权
标题翻译：半导体存储器件及其系统
公开(公告)号：US08208335B2
公开(公告)日：2012-06-26
申请号：US12821515
申请日：2010-06-23
申请人： Dong-Hyuk Lee , Jung-Bae Lee , Doo-Gon Kim , Cheol Kim
发明人： Dong-Hyuk Lee , Jung-Bae Lee , Doo-Gon Kim , Cheol Kim
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/401 , G11C11/406 , G11C11/40618 , G11C11/40622 , G11C29/24 , G11C29/50016 , G11C2211/4061
摘要： A semiconductor memory device includes a cell array unit having a plurality of banks each having a plurality of blocks, and a refresh controller configured to set at least one of the blocks as a test block, perform a refresh operation on the blocks except for the test block in a self-refresh operation period, determine a refresh period of the test block, and then set another one of the blocks as the test block.
摘要翻译：半导体存储器件包括具有多个块的单元阵列单元，每个单元具有多个块，以及刷新控制器，被配置为将至少一个块设置为测试块，对除了测试之外的块执行刷新操作在自刷新操作期间块，确定测试块的刷新周期，然后将另一个块设置为测试块。

17. 发明申请

US20110069572A1 ROW ADDRESS CODE SELECTION BASED ON LOCATIONS OF SUBSTANDARD MEMORY CELLS 有权
标题翻译：基于物理存储器单元的位置选择地址代码
公开(公告)号：US20110069572A1
公开(公告)日：2011-03-24
申请号：US12832208
申请日：2010-07-08
申请人： Dong-Hyuk Lee , Jung-Bae Lee , Ki-Won Park
发明人： Dong-Hyuk Lee , Jung-Bae Lee , Ki-Won Park
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40618 , G11C11/40622 , G11C17/16 , G11C2211/4061
摘要： A memory device identifies memory blocks that contain substandard memory cells. The memory device then determines row address codes to apply to the memory blocks during refresh operations. The row address codes determine which memory blocks of the memory block are refreshed together. The row address codes are designed to ensure that memory blocks having substandard memory cells, which must be refreshed more frequently than other cells, are refreshed together, while memory blocks without substandard memory cells are refreshed together.
摘要翻译：存储器设备识别包含不合标准存储器单元的存储器块。然后，存储器件在刷新操作期间确定应用于存储器块的行地址代码。行地址代码确定存储器块的哪些存储器块被一起刷新。行地址码被设计为确保具有不同于其它单元的频率更新的不合格存储器单元的存储器块被一起刷新，而没有不合格存储器单元的存储器块被刷新在一起。

18. 发明申请

US20100124138A1 Semiconductor memory device having variable-mode refresh operation 审中-公开
标题翻译：具有可变模式刷新操作的半导体存储器件
公开(公告)号：US20100124138A1
公开(公告)日：2010-05-20
申请号：US12585317
申请日：2009-09-11
申请人： Dong-Hyuk Lee , Jung-Bae Lee
发明人： Dong-Hyuk Lee , Jung-Bae Lee
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C8/10 , G11C7/1075 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C2211/4013
摘要： A semiconductor memory device includes a bit line sense amplifier, a bit line pair that includes a bit line and a complementary bit line, the bit line and the complementary bit line of the bit line pair each being coupled to the bit line sense amplifier, a memory cell array having a plurality of memory banks, the memory banks including word lines and a plurality of memory cells, and a word line activation control unit that performs a control to access data corresponding to an externally same address in at least two memory cells by simultaneously activating a predetermined number of word lines from among the word lines sharing the bit line sense amplifier, and the word line activation control unit operates in response to a determination mode allowing signal that is set in accordance with a used memory density.
摘要翻译：半导体存储器件包括位线读出放大器，包括位线和互补位线的位线对，位线对的互补位线与位线读出放大器耦合，具有多个存储体的存储单元阵列，所述存储体包括字线和多个存储器单元，以及字线激活控制单元，其执行控制以通过在至少两个存储器单元中访问对应于外部相同地址的数据进行控制同时从共享位线读出放大器的字线中激活预定数量的字线，并且字线激活控制单元响应于根据所使用的存储器密度设置的确定模式允许信号来操作。

19. 发明申请

US20110202918A1 VIRTUALIZATION APPARATUS FOR PROVIDING A TRANSACTIONAL INPUT/OUTPUT INTERFACE 审中-公开
标题翻译：用于提供交互式输入/输出接口的虚拟化设备
公开(公告)号：US20110202918A1
公开(公告)日：2011-08-18
申请号：US12985926
申请日：2011-01-06
申请人： Chan-Ju Park , Sang-Bum Suh , Dong-Hyuk Lee
发明人： Chan-Ju Park , Sang-Bum Suh , Dong-Hyuk Lee
IPC分类号： G06F9/455
CPC分类号： G06F9/45541
摘要： A virtualization apparatus and method for providing a transactional input/output interface to prevent input/output performance from deteriorating are provided. The virtualization apparatus includes hardware, a virtual machine monitor to support a plurality of operating systems to use the hardware, and a transaction device driver that executes transactions for hardware I/O operation and to provide an interface for executing a transaction for input/output operations to/from the hardware.
摘要翻译：提供一种用于提供事务输入/输出接口以防止输入/输出性能恶化的虚拟化装置和方法。虚拟化装置包括硬件，支持多个操作系统以使用硬件的虚拟机监视器以及执行用于硬件I / O操作的事务的事务设备驱动器，并提供用于执行用于输入/输出操作的事务的接口去/从硬件。

20. 发明授权

US06895777B2 Front suction/discharge type outdoor unit for airconditioner 有权
标题翻译：空气调节器前排吸式室外机
公开(公告)号：US06895777B2
公开(公告)日：2005-05-24
申请号：US10451776
申请日：2003-04-18
申请人： In-Gyu Kim , Young-Ju Bae , Jac-Hyung Koo , Byung-Il Park , Kyeong-Ho Kim , Yang-Ho Kim , Young-Ho Hong , Kyeong-Wook Heo , Kang-Wook Cha , Si-Kyong Sung , Dong-Hyuk Lee , Seong-Min Kang , Tae-Geun Kim
发明人： In-Gyu Kim , Young-Ju Bae , Jac-Hyung Koo , Byung-Il Park , Kyeong-Ho Kim , Yang-Ho Kim , Young-Ho Hong , Kyeong-Wook Heo , Kang-Wook Cha , Si-Kyong Sung , Dong-Hyuk Lee , Seong-Min Kang , Tae-Geun Kim
IPC分类号： F24F5/00 , F24F1/00 , F24F13/00 , F24F13/075 , F24F13/20 , F25D17/06
CPC分类号： F24F1/52 , F24F1/56 , F24F1/60
摘要： The present invention relates to a front suction/discharge type outdoor unit for an air conditioner which can solve problems due to increased capacity and decreased suction air. The front suction/discharge type outdoor unit includes an outdoor unit casing having its one surface externally opened and its other surfaces closed, the inside of which being divided into a suction unit and a discharge unit, a compressor installed in the suction unit of the outdoor unit casing, for compressing a refrigerant gas supplied from an indoor unit through pipe lines, an air-cooled condenser positioned in the suction unit of the outdoor unit casing to face one surface and face two surfaces contacting one surface and being positioned in parallel among the other surfaces, for inducing external air sucked through one surface to gaps from the facing surfaces for heat exchange, and condensing the refrigerant gas from the compressor by external air sucked in the direction of one surface and the facing surfaces, and a cooling fan installed in the discharge unit of the outdoor unit casing, for supplying external air to the air-cooled condenser, and discharging heat exchanged air.
摘要翻译：本发明涉及一种能够解决由于容量增加和吸入空气减少而引起的问题的空调机的前排吸/排气式室外机。前排气型室外机包括室外单元壳体，其一面从外部开口，其另一面封闭，其内部分为抽吸单元和排出单元，压缩机安装在室外抽吸单元单元壳体，用于通过管线压缩从室内单元供给的制冷剂气体;空气冷凝器，其位于室外单元壳体的吸入单元中，面对一个表面并且面对与一个表面接触的两个表面，其它表面用于引导从一个表面吸入的外部空气与相对表面的间隙进行热交换，并且通过沿一个表面和相对表面的方向吸入的外部空气使来自压缩机的制冷剂气体冷凝，以及安装在室外机壳体的排出单元，用于向外部冷却冷凝器供给外部空气，并排出换热空气。

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