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11. 发明授权

US08787002B2 Winding-type solid electrolytic capacitor package structure 有权
标题翻译：绕组式固体电解电容器封装结构
公开(公告)号：US08787002B2
公开(公告)日：2014-07-22
申请号：US13612816
申请日：2012-09-12
申请人： Ching-Feng Lin , Chi-Hao Chiu , Kun-Huang Chang
发明人： Ching-Feng Lin , Chi-Hao Chiu , Kun-Huang Chang
IPC分类号： H01G4/32
CPC分类号： H01G9/151 , H01G9/012 , H01G9/08
摘要： A winding-type solid electrolytic capacitor package structure includes a capacitor unit, a package unit and a conductive unit. The conductive unit includes a winding-type capacitor having a first conductive pin and a second conductive pin. The package unit includes a package body for enclosing the capacitor unit. The conductive unit includes a first conductive terminal electrically connected to the first conductive pin and a second conductive terminal electrically connected to the second conductive pin. The first conductive terminal has a first embedded portion contacting the first conductive pin and enclosed by the package body and a first exposed portion connected to the first embedded portion and exposed from the package body. The second conductive terminal has a second embedded portion contacting the second conductive pin and enclosed by the package body and a second exposed portion connected to the second embedded portion and exposed from the package body.
摘要翻译：卷绕式固体电解电容器封装结构包括电容器单元，封装单元和导电单元。导电单元包括具有第一导电引脚和第二导电引脚的绕组型电容器。封装单元包括用于封闭电容器单元的封装体。导电单元包括电连接到第一导电引脚的第一导电端子和电连接到第二导电引脚的第二导电端子。所述第一导电端子具有接触所述第一导电针并被所述封装主体封闭的第一嵌入部分，以及连接到所述第一嵌入部分并从所述封装主体露出的第一暴露部分。第二导电端子具有接触第二导电引脚并被封装体包围的第二嵌入部分，以及连接到第二嵌入部分并从封装主体露出的第二暴露部分。

12. 发明授权

US08755171B2 Stacked-type solid electrolytic capacitor package structure 有权
标题翻译：堆叠式固体电解电容器封装结构
公开(公告)号：US08755171B2
公开(公告)日：2014-06-17
申请号：US13613098
申请日：2012-09-13
申请人： Ching-Feng Lin , Chi-Hao Chiu , Kun-Huang Chang
发明人： Ching-Feng Lin , Chi-Hao Chiu , Kun-Huang Chang
IPC分类号： H01G2/10 , H01G9/08
CPC分类号： H01G9/012 , H01G9/08 , H01G9/15
摘要： A stacked-type solid electrolytic capacitor package structure includes a capacitor unit, a package unit and a conductive unit. The capacitor unit includes a plurality of capacitors stacked on top of one another. The package unit includes a package body enclosing the capacitors. The package body has a top surface defining a package length, a package width and an effective package, and the package width is substantially between 85% and 95% of the package length. The conductive unit includes a first conductive terminal electrically connected to the positive portion of the capacitor and a second conductive terminal electrically connected to the negative portion of the capacitor. One part of the first conductive terminal and one part of the second conductive terminal are enclosed by the package body, and another part of the first conductive terminal and another part of the second conductive terminal are exposed from the package body.
摘要翻译：叠层型固体电解电容器封装结构包括电容器单元，封装单元和导电单元。电容器单元包括堆叠在彼此顶部的多个电容器。封装单元包括封装电容器的封装体。包装体具有限定包装长度，包装宽度和有效包装的顶表面，并且包装宽度基本上在包装长度的85％至95％之间。导电单元包括电连接到电容器的正部分的第一导电端子和电连接到电容器的负极部分的第二导电端子。第一导电端子的一部分和第二导电端子的一部分被封装体包围，并且第一导电端子的另一部分和第二导电端子的另一部分从封装体露出。

13. 发明授权

US08654511B2 Capacitance unit and stacked solid electrolytic capacitor 有权
标题翻译：电容单元和堆叠固体电解电容器
公开(公告)号：US08654511B2
公开(公告)日：2014-02-18
申请号：US13178464
申请日：2011-07-07
申请人： Chi-Hao Chiu , Ching-Feng Lin , Kun-Huang Chang
发明人： Chi-Hao Chiu , Ching-Feng Lin , Kun-Huang Chang
IPC分类号： H01G5/38
CPC分类号： H01G9/012 , H01G9/10 , H01G9/14 , H01G9/15
摘要： A capacitance unit includes an anode portion, an insulating portion, a cathode portion and a colloid portion. The front end of the anode portion extends to from an anode terminal. The insulating portion surrounds the anode portion and covers a first partial surface of the anode portion. The cathode portion is disposed next to the insulating portion, and the cathode portion covers a second partial surface of the anode portion. The colloid portion is disposed next to the insulating portion, and the colloid portion surrounds the cathode portion and covers a partial surface of the cathode portion.
摘要翻译：电容单元包括阳极部分，绝缘部分，阴极部分和胶体部分。阳极部分的前端从阳极端子延伸。绝缘部分包围阳极部分并且覆盖阳极部分的第一部分表面。阴极部分靠近绝缘部分设置，阴极部分覆盖阳极部分的第二部分表面。胶体部分靠近绝缘部分设置，胶体部分包围阴极部分并覆盖阴极部分的部分表面。

14. 发明申请

US20050101053A1 Quad flat flip chip packaging process and leadframe therefor 有权
标题翻译：四平面倒装芯片封装工艺及其引线框架
公开(公告)号：US20050101053A1
公开(公告)日：2005-05-12
申请号：US10967910
申请日：2004-10-18
申请人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
发明人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
IPC分类号： H01L23/31 , H01L23/495 , H01L21/48
CPC分类号： H01L23/49558 , H01L23/3114 , H01L23/49586 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2224/05599
摘要： A quad flat flip chip packaging process and a leadframe therefor are provided. A sacrificial film is attached on the leads of the leadframe for limiting the extent of bumps when formed and saving the manufacturing cost. Besides, the sacrificial film can be removed from the leadframe after a reflow step. Thus, the delamination between the molding compound material and the leads can be prevented during the molding step.
摘要翻译：提供了一种四平面倒装芯片封装工艺及其引线框架。牺牲膜附着在引线框架的引线上，用于在形成时限制凸块的程度并节省制造成本。此外，在回流步骤之后，牺牲膜可以从引线框架移除。因此，可以在成型步骤期间防止模塑料和导线之间的分层。

15. 发明授权

US07253508B2 Semiconductor package with a flip chip on a solder-resist leadframe 有权
标题翻译：半导体封装在阻焊引线框上具有倒装芯片
公开(公告)号：US07253508B2
公开(公告)日：2007-08-07
申请号：US11014165
申请日：2004-12-17
申请人： Chien Liu , Hsueh-Te Wang , Meng-Jen Wang , Chi-Hao Chiu , Tai-Yuan Huang
发明人： Chien Liu , Hsueh-Te Wang , Meng-Jen Wang , Chi-Hao Chiu , Tai-Yuan Huang
IPC分类号： H01L23/48
CPC分类号： H01L24/17 , H01L23/3107 , H01L23/4334 , H01L23/49548 , H01L23/49558 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L2224/13099 , H01L2224/16245 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/16152 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package includes a flip chip mounted on a plurality of leads and encapsulated by a molding compound. The upper surfaces of the leads includes a plurality of bump-bonding regions at the fan-in ends of the leads, and the lower surfaces of the leads include a plurality of outer connecting regions at the fan-out ends of the leads. A plurality of indentations are formed at the upper surfaces of the leads and adjacent to the corresponding bump-bonding regions so as to avoid solder contamination on the leads. After molding, the indentations are filled with the molding compound. Preferably, the indentations have a reversed “Ω”-shaped profile to prevent bumps of the flip chip from excessively wetting over the other portions of the leads to firmly fix the fan-in ends of the leads.
摘要翻译：半导体封装包括安装在多个引线上并由模塑料封装的倒装芯片。引线的上表面在引线的扇入端处包括多个凸起接合区域，并且引线的下表面在引线的扇出端处包括多个外连接区域。在引线的上表面和相邻的凸起焊接区域附近形成多个压痕，以避免引线上的焊料污染。成型后，用模塑料填充压痕。优选地，凹痕具有反转的“Ω”形轮廓，以防止倒装芯片的凸起在引线的其它部分上过度润湿以牢固地固定引线的扇形端。

16. 发明授权

US07022551B2 Quad flat flip chip packaging process and leadframe therefor 有权
标题翻译：四平面倒装芯片封装工艺及其引线框架
公开(公告)号：US07022551B2
公开(公告)日：2006-04-04
申请号：US10967910
申请日：2004-10-18
申请人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
发明人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
IPC分类号： H01L21/44
CPC分类号： H01L23/49558 , H01L23/3114 , H01L23/49586 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2224/05599
摘要： A quad flat flip chip packaging process and a leadframe therefor are provided. A sacrificial film is attached on the leads of the leadframe for limiting the extent of bumps when formed and saving the manufacturing cost. Besides, the sacrificial film can be removed from the leadframe after a reflow step. Thus, the delamination between the molding compound material and the leads can be prevented during the molding step.
摘要翻译：提供了一种四平面倒装芯片封装工艺及其引线框架。牺牲膜附着在引线框架的引线上，用于在形成时限制凸块的程度并节省制造成本。此外，在回流步骤之后，牺牲膜可以从引线框架移除。因此，可以在成型步骤期间防止模塑料和引线之间的分层。

17. 发明申请

US20050104167A1 Flip-chip type quad flat package and leadframe 有权
标题翻译：倒装片式四方扁平封装和引线框架
公开(公告)号：US20050104167A1
公开(公告)日：2005-05-19
申请号：US10979881
申请日：2004-11-01
申请人： Hsueh-Te Wang , Meng-Jen Wang , Chi-Hao Chiu , Chien Liu
发明人： Hsueh-Te Wang , Meng-Jen Wang , Chi-Hao Chiu , Chien Liu
IPC分类号： H01L23/31 , H01L23/495
CPC分类号： H01L23/4951 , H01L23/3107 , H01L23/4952 , H01L23/49541 , H01L23/49568 , H01L2224/05571 , H01L2224/05573 , H01L2224/16
摘要： A flip-chip type quad flat package and a leadframe. The leadframe comprsies a bump-connecting area and a non-connecting area. The maximum width of the bump-connecting area is larger than the width of the non-connecting area. A bump is limited to the bump-connecting area after performing a reflow process so that the bumps are prevented from collapsing, the manufacturing cost is reduced and the process is simplified.
摘要翻译：倒装型四边形扁平封装和引线框架。引线框架包括凸块连接区域和非连接区域。突起连接区域的最大宽度大于非连接区域的宽度。在进行回流处理之后，凸块被限制在凸块连接区域，从而防止凸块塌陷，制造成本降低，工艺简化。

18. 发明申请

US20070085218A1 FLIP CHIP PACKAGE 审中-公开
标题翻译： FLIP芯片包
公开(公告)号：US20070085218A1
公开(公告)日：2007-04-19
申请号：US11563029
申请日：2006-11-24
申请人： Yu-Wen Chen , Chih-Ming Chung , Chi-Hao Chiu
发明人： Yu-Wen Chen , Chih-Ming Chung , Chi-Hao Chiu
IPC分类号： H01L23/48
CPC分类号： H01L24/28 , H01L21/563 , H01L23/36 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/73203 , H01L2224/83102 , H01L2224/92125 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/3025 , H01L2924/3512 , H01L2924/00 , H01L2224/05599
摘要： A flip chip package structure is provided. A chip is electrically connected to a substrate. A heat sink is attached to the backside of the chip. The heat sink has at least a through hole located at a peripheral region and laterally adjacent to the chip. A dispensing process is carried out to deliver an underfill material via the through hole such that the space between the chip and the substrate is filled. The underfill material also extends to cover a portion of the heat sink so that the heat sink and the substrate are connected together. The underfill material is cured to fix the heat sink, the substrate and the chip in position.
摘要翻译：提供了一种倒装芯片封装结构。芯片电连接到基板。散热片连接到芯片的背面。散热器至少具有位于周边区域并且横向邻近芯片的通孔。进行分配处理以通过通孔输送底部填充材料，使得填充芯片和基板之间的空间。底部填充材料还延伸以覆盖散热器的一部分，使得散热器和基板连接在一起。固化底部填充材料以将散热器，基板和芯片固定就位。

19. 发明授权

US07164202B2 Quad flat flip chip package and leadframe thereof 有权
标题翻译：四平面倒装芯片封装及其引线框架
公开(公告)号：US07164202B2
公开(公告)日：2007-01-16
申请号：US10904517
申请日：2004-11-15
申请人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
发明人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
IPC分类号： H01L23/48
CPC分类号： H01L23/49551 , H01L23/3114 , H01L23/4334 , H01L23/49548 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01322 , H01L2924/18161 , H01L2224/05599
摘要： A quad flat flip chip package and a leadframe therefor are provided. A bump connection part is defined by bending or etching the leads of the leadframe. Thus, the bump formed after a reflow process is limited within the bump connection part, and the collapse of the bump can be prevented. Moreover, and the manufacturing costs of the package can be decreased and the process thereof can be simplified.
摘要翻译：提供了四平面倒装芯片封装及其引线框。通过弯曲或蚀刻引线框架的引线来限定凸块连接部分。因此，在回流焊接工序之后形成的凸点被限制在凸块连接部内，并且可以防止凸块的塌陷。此外，可以减少包装的制造成本，并且可以简化其处理。

20. 发明申请

US20050156296A1 QUAD FLAT FLIP CHIP PACKAGE AND LEADFRAME THEREOF 有权
标题翻译：四边形平板纸芯片包装和铅笔
公开(公告)号：US20050156296A1
公开(公告)日：2005-07-21
申请号：US10904517
申请日：2004-11-15
申请人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
发明人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
IPC分类号： H01L23/31 , H01L23/433 , H01L23/495
CPC分类号： H01L23/49551 , H01L23/3114 , H01L23/4334 , H01L23/49548 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01322 , H01L2924/18161 , H01L2224/05599
摘要： A quad flat flip chip package and a leadframe therefor are provided. A bump connection part is defined by bending or etching the leads of the leadframe. Thus, the bump formed after a reflow process is limited within the bump connection part, and the collapse of the bump can be prevented. Moreover, and the manufacturing costs of the package can be decreased and the process thereof can be simplified.
摘要翻译：提供了四平面倒装芯片封装及其引线框。通过弯曲或蚀刻引线框架的引线来限定凸块连接部分。因此，在回流焊接工序之后形成的凸点被限制在凸块连接部内，并且可以防止凸块的塌陷。此外，可以减少包装的制造成本，并且可以简化其处理。

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