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11. 发明申请

US20110302544A1 POST-PLACEMENT CELL SHIFTING 失效
标题翻译：后置放电细胞移位
公开(公告)号：US20110302544A1
公开(公告)日：2011-12-08
申请号：US12796550
申请日：2010-06-08
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块。扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。扩张器也可能使这些细胞膨胀并合法化。

12. 发明授权

US08015532B2 Optimal timing-driven cloning under linear delay model 有权
标题翻译：线性延迟模型下最优时序驱动克隆
公开(公告)号：US08015532B2
公开(公告)日：2011-09-06
申请号：US11938824
申请日：2007-11-13
申请人： Charles J. Alpert , Zhuo Li , David A. Papa , Chin Ngai Sze
发明人： Charles J. Alpert , Zhuo Li , David A. Papa , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A timing-driven cloning method iteratively partitions sinks of the net into different sets of clusters and for each set computes a figure of merit for a cloned gate location which optimizes timing based on linear delay, that is, a delay proportional to the distance between the cloned gate location and the sinks. The set having the highest figure of merit is selected as the best solution. The original gate may also be moved to a timing-optimized location. The sinks are advantageously partitioned using boundaries of Voronoi polygons defined by a diamond region surrounding the original gate, or vice versa. The figure of merit may be for example worst slack, a sum of slacks at the sinks in the second cluster, or a linear combination of worst slack and sum of the slacks.
摘要翻译：定时驱动的克隆方法将网络的宿迭代地分成不同的群集，并且对于每个集合来计算克隆的门位置的品质因数，其优化基于线性延迟的定时，即，与克隆门位置和汇。选择具有最高品质因数的集合作为最佳解决方案。原始门也可以移动到定时优化的位置。有利地使用由围绕原始门的金刚石区域定义的Voronoi多边形的边界来划分水槽，反之亦然。品质因数可以是例如最差的松弛度，第二组中的汇的松弛度的总和，或者最差的松弛和松弛的总和的线性组合。

13. 发明申请

US20100223586A1 TECHNIQUES FOR PARALLEL BUFFER INSERTION 有权
标题翻译：并行缓存插入技术
公开(公告)号：US20100223586A1
公开(公告)日：2010-09-02
申请号：US12395373
申请日：2009-02-27
申请人： Zhuo Li , Charles J. Alpert , Damir Jamsek , Chin Ngai Sze , Ying Zhou
发明人： Zhuo Li , Charles J. Alpert , Damir Jamsek , Chin Ngai Sze , Ying Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The present disclosure is directed to a method for determining a plurality of buffer insertion locations in a net for an integrated circuit design. The method may comprise calculating a plurality of resistive-capacitive (RC) influences in parallel, each RC influence corresponding to one of a plurality of buffering options available for a first sub-tree for the addition of a wire segment to the first sub-tree; updating the plurality of RC influences for the addition of a buffer for the first sub-tree, the buffer comprising one of a plurality of buffer types; and merging the first sub-tree with a second sub-tree in parallel by grouping the plurality of buffering options available for the first sub-tree and a plurality of buffering options available for the second sub-tree into a plurality of merging groups, and merging at least two groups of the plurality of merging groups in parallel.
摘要翻译：本公开涉及一种用于确定用于集成电路设计的网络中的多个缓冲器插入位置的方法。该方法可以包括并行计算多个电阻 - 电容（RC）影响，每个RC影响对应于可用于第一子树的多个缓冲选项之一，用于将线段添加到第一子树 ; 更新所述多个RC影响以添加所述第一子树的缓冲器，所述缓冲器包括多个缓冲器类型之一; 以及通过将可用于所述第一子树的所述多个缓冲选项和可用于所述第二子树的多个缓冲选项分组成多个合并组来并行地将所述第一子树与第二子树合并，以及合并至少两组多个合并组。

14. 发明申请

US20090089721A1 METHOD FOR INCREMENTAL, TIMING-DRIVEN, PHYSICAL-SYNTHESIS OPTIMIZATION 审中-公开
标题翻译：增量，时序驱动，物理综合优化的方法
公开(公告)号：US20090089721A1
公开(公告)日：2009-04-02
申请号：US11866231
申请日：2007-10-02
申请人： Charles J. Alpert , Arvind K. Karandikar , Zhuo Li , Gijoon Nam , David A. Papa , Chin Ngai Sze
发明人： Charles J. Alpert , Arvind K. Karandikar , Zhuo Li , Gijoon Nam , David A. Papa , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Rip Up and Move Boxes with Linear Evaluation (RUMBLE) utility identifies movable gate(s) for timing-driven optimization. The RUMBLE utility isolates an original subcircuit corresponding to the movable gate(s) and builds an unbuffered model of the original subcircuit. Notably, a new optimized placement of the movable gate is yielded to optimize the timing (i.e., maximize the minimum slack) of the original subcircuit, while accounting for future interconnect optimizations. The new subcircuit containing the new optimized gate placement and interconnect optimization is evaluated as to whether a timing degradation exists in the new subcircuit. If a timing degradation exists in the new subcircuit, the RUMBLE utility can restore an original subcircuit and a timing state associated with the original subcircuit.
摘要翻译：一种用于优化物理合成流中子电路的逻辑门的布置的方法，数据处理系统和计算机程序产品。具有线性评估（RUMBLE）功能的移动和移动盒识别用于定时驱动优化的可移动门。 RUMBLE实用程序隔离与可移动门对应的原始子电路，并构建原始子电路的无缓冲模型。值得注意的是，产生了可移动门的新优化布置，以优化原始子电路的定时（即，最大化最小松弛），同时考虑到将来的互连优化。评估包含新优化的栅极布局和互连优化的新子电路是否存在新的子电路中的定时劣化。如果新的子电路中存在定时降级，则RUMBLE实用程序可以恢复原始子电路和与原始子电路相关联的定时状态。

15. 发明授权

US08667441B2 Clock optimization with local clock buffer control optimization 有权
标题翻译：时钟优化与本地时钟缓冲控制优化
公开(公告)号：US08667441B2
公开(公告)日：2014-03-04
申请号：US12947445
申请日：2010-11-16
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , David A. Papa , Chin Ngai Sze , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , David A. Papa , Chin Ngai Sze , Natarajan Viswanathan
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/505 , G06F2217/62
摘要： A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.
摘要翻译：提供了一种用于通过本地时钟缓冲器控制优化进行码头优化的物理综合工具。物理合成流程包括延迟时钟路由的曝光，直到时钟优化放置阶段为止。物理综合工具克隆了第一个本地时钟缓冲区。然后，物理综合工具对整个设计运行时序分析，以计算这一必然破坏性步骤的影响。在克隆本地时钟缓冲器之后，物理综合工具增加了一个额外的优化步骤来对驱动本地时钟缓冲器的控制信号进行目标。该优化步骤可以包括锁存克隆，定时驱动放置，缓冲器插入和重新供电。该流程减轻了高扇出网络，并显着提高了进入时钟优化布局的时间。放置后，物理综合工具将锁存器和本地时钟缓冲器固定到位，插入时钟路由并释放本地时钟缓冲区。

16. 发明申请

US20100257498A1 INCREMENTAL TIMING OPTIMIZATION AND PLACEMENT 有权
标题翻译：增量时序优化和放置
公开(公告)号：US20100257498A1
公开(公告)日：2010-10-07
申请号：US12416754
申请日：2009-04-01
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Disclosed is a computer implemented method, data processing system, and computer program product to optimize, incrementally, a circuit design. An Electronic Design Automation (EDA) system receives a plurality of nets wherein each net is comprised of at least one pin. Each pin is linked to a net to form a path of at least a first pin and a second pin, wherein the first pin is a member of a first net. The second pin can be a member of a second net, and the path is associated with a slack. The EDA system determines whether the path is a critical path based on the slack. The EDA system reduces at least one wire length of the path, responsive to a determination that the path is a critical path. The EDA system moves a non-critical component in order to reduce at least one wire length of the nets that include pins of a non-critical component, responsive to reducing at least one wire length of the path, wherein the non-critical component lacks pins on a critical path. The EDA system legalizes the components on a net having a pin selected from the first pin and the second pin. The EDA system determines whether a component is a non-critical component. The EDA system, responsive to a determination that component is a non-critical component, legalizes the non-critical component. The EDA system incrementally optimizes a time delay of the plurality of paths, responsive to legalizing.
摘要翻译：公开了一种计算机实现的方法，数据处理系统和计算机程序产品，以优化，递增地进行电路设计。电子设计自动化（EDA）系统接收多个网络，其中每个网络由至少一个引脚组成。每个销连接到网以形成至少第一销和第二销的路径，其中第一销是第一网的成员。第二个引脚可以是第二个网络的一个成员，并且该路径与一个松弛相关联。 EDA系统确定路径是否是基于松弛的关键路径。响应于确定路径是关键路径，EDA系统减少路径的至少一个线长度。 EDA系统移动非关键部件，以便响应于减少路径的至少一个线长度来减少包括非关键部件的引脚的网络的至少一个线长度，其中非关键部件缺少关键路径上的引脚。 EDA系统使具有从第一引脚和第二引脚选择的引脚的网络上的部件合法化。 EDA系统确定组件是否是非关键组件。 EDA系统响应于组件是非关键组件的确定，使非关键组件合法化。响应于合法化，EDA系统递增地优化多个路径的时间延迟。

17. 发明授权

US07761832B2 Method for incremental, timing-driven, physical-synthesis optimization under a linear delay model 有权
标题翻译：线性延迟模型下增量，时序驱动，物理综合优化的方法
公开(公告)号：US07761832B2
公开(公告)日：2010-07-20
申请号：US11941418
申请日：2007-11-16
申请人： Charles J. Alpert , Zhuo Li , Tao Luo , David A. Papa , Chin Ngai Sze
发明人： Charles J. Alpert , Zhuo Li , Tao Luo , David A. Papa , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Pyramids utility identifies and selects movable gate(s) for timing-driven optimization. A delay pyramid and a required arrival time (RAT) surface are generated for each net in the selected subcircuit. A slack pyramid for each net is generated from the difference between the RAT surface and delay pyramid of each net. The slack pyramids are grown and tested using test points to generate a worst-case slack region based on a plurality of slack pyramids in the selected subcircuit. The worst-case slack region is mapped on a placement region and a set of coordinates representing the optimal locations of the movable element(s) in the placement region are determined and outputted.
摘要翻译：一种用于优化物理合成流中子电路的逻辑门的布置的方法，数据处理系统和计算机程序产品。金字塔实用程序识别并选择可移动门以进行时序优化。为所选择的子电路中的每个网络生成延迟金字塔和所需的到达时间（RAT）表面。从每个网络的RAT表面和延迟金字塔之间的差异产生每个网络的松散金字塔。使用测试点生长和测试松散的金字塔，以基于所选择的子电路中的多个松散金字塔产生最差情况的松弛区域。最坏情况的松弛区域映射在放置区域上，并且确定并输出表示放置区域中的可移动元件的最佳位置的坐标系。

18. 发明申请

US20080288905A1 Method and Apparatus for Congestion Based Physical Synthesis 审中-公开
标题翻译：基于拥塞的物理综合方法与装置
公开(公告)号：US20080288905A1
公开(公告)日：2008-11-20
申请号：US11748514
申请日：2007-05-15
申请人： Charles J. Alpert , Arvind K. Karandikar , Zhuo Li , Chin Ngai Sze
发明人： Charles J. Alpert , Arvind K. Karandikar , Zhuo Li , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A computer implemented method, apparatus, and computer usable program product for modifying a circuit design are provided in the illustrative embodiments. A set of candidate areas within the circuit design is identified for making a change to the circuit design. A cost associated with each candidate area in the set of candidate areas is determined to form a set of costs. The cost associated with a candidate area is the cost of making the change to the circuit design in the candidate area. Using the set of costs, a candidate area is selected from the set of candidate areas in which to make the change to the circuit design.
摘要翻译：在说明性实施例中提供了用于修改电路设计的计算机实现的方法，装置和计算机可用程序产品。确定电路设计中的一组候选区域用于改变电路设计。与候选区域集合中的每个候选区域相关联的成本被确定以形成一组成本。与候选区域相关的成本是对候选区域中的电路设计进行更改的成本。使用一组成本，从对电路设计进行改变的候选区域集合中选择候选区域。

19. 发明授权

US08589848B2 Datapath placement using tiered assignment 有权
标题翻译： Datapath放置使用分层分配
公开(公告)号：US08589848B2
公开(公告)日：2013-11-19
申请号：US13451382
申请日：2012-04-19
申请人： Charles J. Alpert , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
发明人： Charles J. Alpert , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Datapath placement defines tiers for placement sets of a cell cluster, assigns cells to the tiers constrained by the datapath width, and then orders cells within each tier. Clusters are identified using machine-learning based datapath extraction. Datapath width is determined by computing a size of a bounding box for cells in the cluster. Placement sets are identified using a breadth-first search beginning with input cells for the cluster. Tiers are initially defined using logic depth assignment. A cell may be assigned to a tier by pulling the cell from the next higher tier to fill an empty location or by pushing an excess cell into the next higher tier. Cells are ordered within each tier using greedy cell assignment according to a wirelength cost function. The datapath placement can be part of an iterative process which applies spreading constraints to the cluster based on computed congestion information.
摘要翻译：数据路径布局定义了单元格集群的布局集合的层次，将单元格分配给由数据路径宽度约束的层，然后在每个层中排序单元格。使用基于机器学习的数据路径提取来识别群集。数据路径宽度通过计算群集中的单元格的边界框的大小来确定。使用从集群的输入单元开始的宽度优先搜索来标识放置集。最初使用逻辑深度分配定义层次。可以通过从下一较高层拉动单元以填充空位或通过将多余单元推入下一较高层来将单元分配给层。根据线长成本函数，使用贪心小区分配在每个层中对单元进行排序。数据路径放置可以是迭代过程的一部分，其基于计算的拥塞信息将扩展约束应用于集群。

20. 发明申请

US20130283225A1 DATAPATH PLACEMENT USING TIERED ASSIGNMENT 有权
标题翻译：使用方式分配的DATAPATH放置
公开(公告)号：US20130283225A1
公开(公告)日：2013-10-24
申请号：US13451382
申请日：2012-04-19
申请人： Charles J. Alpert , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
发明人： Charles J. Alpert , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Datapath placement defines tiers for placement sets of a cell cluster, assigns cells to the tiers constrained by the datapath width, and then orders cells within each tier. Clusters are identified using machine-learning based datapath extraction. Datapath width is determined by computing a size of a bounding box for cells in the cluster. Placement sets are identified using a breadth-first search beginning with input cells for the cluster. Tiers are initially defined using logic depth assignment. A cell may be assigned to a tier by pulling the cell from the next higher tier to fill an empty location or by pushing an excess cell into the next higher tier. Cells are ordered within each tier using greedy cell assignment according to a wirelength cost function. The datapath placement can be part of an iterative process which applies spreading constraints to the cluster based on computed congestion information.
摘要翻译：数据路径布局定义了单元格集群的布局集合的层次，将单元格分配给由数据路径宽度约束的层，然后在每个层中排序单元格。使用基于机器学习的数据路径提取来识别群集。数据路径宽度通过计算群集中的单元格的边界框的大小来确定。使用从集群的输入单元开始的宽度优先搜索来标识放置集。最初使用逻辑深度分配定义层次。可以通过从下一较高层拉动单元以填充空位或通过将多余单元推入下一较高层来将单元分配给层。根据线长成本函数，使用贪心小区分配在每个层中对单元进行排序。数据路径放置可以是迭代过程的一部分，其基于计算的拥塞信息将扩展约束应用于集群。

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