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11. 发明授权

US5292683A Method of isolating semiconductor devices and arrays of memory integrated circuitry 失效
标题翻译：隔离半导体器件和存储器集成电路阵列的方法
公开(公告)号：US5292683A
公开(公告)日：1994-03-08
申请号：US71752
申请日：1993-06-09
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L21/76 , H01L21/108 , H01L21/762 , H01L21/8234 , H01L21/8242 , H01L27/108 , H01L29/78 , H01L21/304
CPC分类号： H01L27/10852 , H01L21/76224 , H01L21/823481 , Y10S148/05
摘要： A semiconductor processing device isolation method includes: a) providing non-LOCOS insulating device isolation blocks by trench and refill technique on a substrate to define recessed moat volume therebetween; b) providing gate dielectric within the moat volume; c) providing a layer of electrically conductive material over the substrate and gate dielectric to a thickness sufficient to completely fill the moat volume between adjacent isolation blocks; d) chemical-mechanical polishing the layer of electrically conductive material to provide a planarized upper electrically conductive material surface; e) photopatterning and etching the layer of electrically conductive material to provide an electrically conductive runner which overlies a plurality of the isolation blocks and to selectively remove the electrically conductive material from within selected regions of moat volume to define field effect transistor gates within the moat volume; and f) providing conductivity enhancing impurity through the selected regions of moat volume into the substrate to define source/drain regions adjacent the field effect transistor gates. The invention also includes an array of memory integrated circuitry.
摘要翻译：半导体处理器件隔离方法包括：a）通过沟槽和再填充技术在衬底上提供非LOCOS绝缘器件隔离块，以在其间限定凹陷的沟槽体积; b）在护城河容积内提供栅极电介质; c）在衬底和栅极电介质上提供一层导电材料，其厚度足以完全填充相邻隔离块之间的护城河体积; d）化学机械抛光导电材料层以提供平坦化的上导电材料表面; e）对导电材料层进行光图案化和蚀刻，以提供覆盖在多个隔离块上的导电浇道，并且选择性地从导流槽体积的选定区域内去除导电材料，以在护城河体积内限定场效应晶体管栅极 ; 以及f）通过所选择的沟槽体积的区域提供导电性增强杂质到衬底中以限定与场效应晶体管栅极相邻的源极/漏极区域。本发明还包括一组存储器集成电路。

12. 发明授权

US07282447B2 Method for an integrated circuit contact 失效
标题翻译：集成电路接触方法
公开(公告)号：US07282447B2
公开(公告)日：2007-10-16
申请号：US10923060
申请日：2004-08-19
申请人： Charles H Dennison , Trung T. Doan
发明人： Charles H Dennison , Trung T. Doan
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The process may be repeated during the formation of multilevel metal integrated circuits.
摘要翻译：在集成电路和器件的制造中提供用于形成垂直触点的工艺。该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。该方法包括在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。在形成多级金属集成电路期间可以重复该过程。

13. 发明授权

US5391511A Semiconductor processing method of producing an isolated polysilicon lined cavity and a method of forming a capacitor 失效
标题翻译：用于制造隔离多晶硅衬里腔的半导体加工方法和形成电容器的方法
公开(公告)号：US5391511A
公开(公告)日：1995-02-21
申请号：US891
申请日：1993-01-05
申请人： Trung T. Doan , Charles H. Dennison
发明人： Trung T. Doan , Charles H. Dennison
IPC分类号： H01L21/02 , H01L21/321 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L21/265
CPC分类号： H01L27/10817 , H01L21/02074 , H01L21/321 , H01L21/3212 , H01L21/76885 , H01L21/76889 , H01L27/10852 , H01L28/91 , Y10S438/906
摘要： A semiconductor processing includes: a) providing an area atop a semiconductor wafer to which electrical connection to a polysilicon containing component is to be made; b) providing a layer of first material atop the semiconductor wafer, the first material layer having an upper surface; c) providing a contact opening in the layer of first material to the area, the contact opening having a selected open cross dimension; d) providing a layer of polysilicon to a selected thickness atop the layer of first material and within the contact opening to contact the area, the selected thickness being less than one-half the open dimension such that polysilicon less than completely fills the contact opening and thereby defines an outwardly open polysilicon lined cavity; e) with the wafer having the polysilicon lined cavity outwardly open, chemical mechanical polishing with a chemical mechanical polishing slurry the polysilicon atop the first material layer to the upper first material layer surface to define an isolated polysilicon lined cavity; and f) removing chemical mechanical polishing slurry residuals from the outwardly open polysilicon lined cavity.
摘要翻译：一种半导体处理方法包括：a）在半导体晶片的顶部提供一个与要制造含多晶硅的元件电连接的区域; b）在半导体晶片的顶部提供第一材料层，第一材料层具有上表面; c）在所述区域的第一材料层中提供接触开口，所述接触开口具有选定的开放交叉尺寸; d）在所述第一材料层顶部和所述接触开口顶部提供选定厚度的多晶硅层以接触所述区域，所述选定厚度小于所述开口尺寸的一半，使得多晶硅不足以完全填充所述接触开口和从而限定向外开放的多晶硅衬里腔; e）当所述晶片具有向外打开的多晶硅衬里的空腔时，化学机械抛光通过化学机械抛光将多晶硅顶部到第一材料层表面以限定隔离的多晶硅衬里腔; 以及f）从向外开放的多晶硅衬里腔体去除化学机械抛光浆料残留物。

14. 发明申请

US20100019388A1 METHOD FOR AN INTEGRATED CIRCUIT CONTACT 失效
标题翻译：集成电路联系方法
公开(公告)号：US20100019388A1
公开(公告)日：2010-01-28
申请号：US12565280
申请日：2009-09-23
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L23/48 , H01L21/3065
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process for forming vertical contacts in the manufacture of integrated circuits and devices eliminating the need for precise mask alignment and allowing the etching of the contact hole controlled independent of the etching of the interconnect trough that may be repeated during the formation of multilevel integrated circuits. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole.
摘要翻译：在集成电路和器件的制造中形成垂直触点的过程，消除了精确掩模对准的需要，并允许蚀刻接触孔，独立于在形成多级集成电路期间可能重复的互连槽的蚀刻。该方法包括在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。

15. 发明授权

US07569485B2 Method for an integrated circuit contact 失效
标题翻译：集成电路接触方法
公开(公告)号：US07569485B2
公开(公告)日：2009-08-04
申请号：US10923587
申请日：2004-08-19
申请人： Charles H Dennison , Trung T. Doan
发明人： Charles H Dennison , Trung T. Doan
IPC分类号： H01L21/311 , H01L21/4763
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.
摘要翻译：在集成电路和器件的制造中提供用于形成垂直触点的工艺。该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。该方法包括以下步骤：在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。在形成多级金属集成电路期间，可以重复上述过程一次或多次。

16. 发明授权

US07276448B2 Method for an integrated circuit contact 失效
标题翻译：集成电路接触方法
公开(公告)号：US07276448B2
公开(公告)日：2007-10-02
申请号：US10923242
申请日：2004-08-19
申请人： Charles H Dennison , Trung T. Doan
发明人： Charles H Dennison , Trung T. Doan
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.
摘要翻译：在集成电路和器件的制造中提供用于形成垂直触点的工艺。该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。该方法包括在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。在形成多级金属集成电路期间可以重复上述过程。

17. 发明授权

US5858877A Self-aligned process for making contacts to silicon substrates during the manufacture of integrated circuits therein 失效
标题翻译：在其中制造集成电路期间与硅衬底接触的自对准工艺
公开(公告)号：US5858877A
公开(公告)日：1999-01-12
申请号：US786482
申请日：1997-01-21
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L21/768 , H01L21/306
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multi-level metal integrated circuits.
摘要翻译：在集成电路的制造中形成垂直触点的工艺以及如此制造的器件。该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。该方法包括以下步骤：在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。在形成多级金属集成电路期间，可以重复上述过程一次或多次。

18. 发明授权

US5651855A Method of making self aligned contacts to silicon substrates during the manufacture of integrated circuits 失效
标题翻译：在制造集成电路期间制造与硅衬底的自对准接触的方法
公开(公告)号：US5651855A
公开(公告)日：1997-07-29
申请号：US626651
申请日：1996-04-01
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L21/768 , H01L21/306
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multi-level metal integrated circuits.
摘要翻译：在集成电路的制造中形成垂直触点的工艺以及如此制造的器件。该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。该方法包括以下步骤：在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。在形成多级金属集成电路期间，可以重复上述过程一次或多次。

19. 发明授权

US08384192B2 Methods for forming small-scale capacitor structures 有权
标题翻译：形成小型电容器结构的方法
公开(公告)号：US08384192B2
公开(公告)日：2013-02-26
申请号：US13047430
申请日：2011-03-14
申请人： Lingyi A. Zheng , Trung T. Doan , Lyle D. Breiner , Er-Xuan Ping , Kevin L. Beaman , Ronald A. Weimer , Cem Basceri , David J. Kubista
发明人： Lingyi A. Zheng , Trung T. Doan , Lyle D. Breiner , Er-Xuan Ping , Kevin L. Beaman , Ronald A. Weimer , Cem Basceri , David J. Kubista
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , H01L21/3141 , H01L27/10852 , H01L28/60 , H01L28/84
摘要： The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 Å.
摘要翻译：本公开提供小尺寸电容器（例如，DRAM电容器）以及形成这种电容器的方法。一个示例性实施例提供了一种制造电容器的方法，该电容器包括顺序地形成第一电极，电介质层和第二电极。可以通过以下方式形成至少一个电极：a）使两个前体反应以第一沉积速率沉积第一导电层，以及b）通过沉积一个前体的前体层以第二较低沉积速率沉积第二导电层至少一层单层，并将该前体层暴露于另一种前体以形成纳米层反应产物。第二导电层可以与介电层接触并具有不大于约的厚度。

20. 发明授权

US08124491B2 Container capacitor structure and method of formation thereof 失效
标题翻译：集装箱电容器结构及其形成方法
公开(公告)号：US08124491B2
公开(公告)日：2012-02-28
申请号：US12547197
申请日：2009-08-25
申请人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
发明人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10817 , H01L27/10852 , H01L27/10888 , H01L28/65 , Y10S257/905
摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.
摘要翻译：公开了一种容器电容器结构及其构造方法。蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

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