专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20110317480A1 PHASE CHANGE MEMORY CODING 有权
标题翻译：相变存储器编码
公开(公告)号：US20110317480A1
公开(公告)日：2011-12-29
申请号：US12823508
申请日：2010-06-25
申请人： HSIANG-LAN LUNG , Ming Hsiu Lee , Yen-Hao Shih , Tien-Yen Wang , Chao-I Wu
发明人： HSIANG-LAN LUNG , Ming Hsiu Lee , Yen-Hao Shih , Tien-Yen Wang , Chao-I Wu
IPC分类号： G11C11/00 , H01L21/06
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/0092
摘要： An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.
摘要翻译：集成电路相变存储器可以通过在一些单元和存储器中引起第一电阻状态以及存储器中的第二电阻状态以及存储器中的一些其他单元来表示数据集而被预编码。在对数据集进行编码之后，将集成电路相变存储器安装在基板上。在安装集成电路相变存储器之后，通过感测第一和第二电阻状态以及将第一电阻状态下的单元改变为第三电阻状态并将第二电阻状态的单元改变为第四电阻状态来读取数据组。第一和第二电阻状态在焊接或其他热循环过程之后保持感测裕度。第三和第四电阻状态的特征在于能够使用更高速度和更低功率的转换，适用于电路的任务功能。

12. 发明申请

US20110255349A1 METHOD OF OPERATING NON-VOLATILE MEMORY CELL 有权
标题翻译：操作非易失性记忆体的方法
公开(公告)号：US20110255349A1
公开(公告)日：2011-10-20
申请号：US13168536
申请日：2011-06-24
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C16/10
CPC分类号： H01L21/28282 , G11C16/0408 , G11C16/0466 , G11C16/107 , H01L29/78654 , H01L29/792
摘要： A method of operating a memory cell for 3D array of this invention is described as follows. Carriers of a first type are injected into a charge storage layer of the memory cell by applying a double-side biased (DSB) voltage to double sides of the memory cell. Carriers of a second type are injected into the charge storage layer by applying FN voltages.
摘要翻译：本发明的3D阵列的存储单元的操作方法如下。通过在存储单元的双面施加双面偏置（DSB）电压将第一类型的载体注入存储单元的电荷存储层。通过施加FN电压将第二类型的载体注入电荷存储层。

13. 发明授权

US07986564B2 High second bit operation window method for virtual ground array with two-bit memory cells 有权
标题翻译：具有两位存储单元的虚拟接地阵列的高二位操作窗口方法
公开(公告)号：US07986564B2
公开(公告)日：2011-07-26
申请号：US12233904
申请日：2008-09-19
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C16/04
CPC分类号： H01L21/28282 , G11C16/0475 , G11C16/0491 , H01L27/11568 , H01L29/7923
摘要： A non-volatile VG memory array employing memory semiconductor cells capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in associating with at least one electrical insulating layer, such as an oxide, is disclosed. Bit lines of the memory array are capable of transmitting positive voltage to reach the source/drain regions of the memory cells of the array. A method that includes the hole injection erasure of the memory cells of the array that lowers the voltage threshold of the memory cells to a value lower than the initial voltage threshold of the cells is disclosed. The hole injection induced lower voltage threshold reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened. The programming and read steps reduce leakage current of the memory cells in the array.
摘要翻译：公开了一种采用存储器半导体单元的非易失性VG存储器阵列，该存储器半导体单元能够存储与至少一个电绝缘层（例如氧化物）相结合的分层的非导电电荷俘获电介质（例如氮化硅）的两比特信息。。存储器阵列的位线能够传输正电压以到达阵列的存储器单元的源极/漏极区域。公开了一种方法，其包括将阵列的存储单元的空穴注入擦除将存储单元的电压阈值降低到低于单元的初始电压阈值的值。空穴注入诱导的较低电压阈值降低了第二位效应，使得位的编程和未编程电压阈值之间的操作窗口变宽。编程和读取步骤减少阵列中存储单元的泄漏电流。

14. 发明授权

US07947607B2 Apparatus and associated method for making a virtual ground array structure that uses inversion bit lines 有权
标题翻译：用于制造使用反转位线的虚拟接地阵列结构的装置和相关方法
公开(公告)号：US07947607B2
公开(公告)日：2011-05-24
申请号：US12342837
申请日：2008-12-23
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： H01L21/311
CPC分类号： G11C16/16 , G11C16/0466 , G11C16/12 , H01L27/0207 , H01L27/115 , H01L27/11568 , Y10S438/954
摘要： A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging.
摘要翻译：虚拟接地阵列结构使用反转位线，以消除对注入位线的需要。结果，可以减小电池尺寸，这可以提供更大的密度和更小的封装。

15. 发明申请

US20100328996A1 PHASE CHANGE MEMORY HAVING ONE OR MORE NON-CONSTANT DOPING PROFILES 有权
标题翻译：具有一个或多个不间断的配置文件的相位更改记忆
公开(公告)号：US20100328996A1
公开(公告)日：2010-12-30
申请号：US12729837
申请日：2010-03-23
申请人： YEN-HAO SHIH , Huai-Yu Cheng , Chieh-Fang Chen , Chao-I Wu , Ming-Hsiu Lee , Hsiang-Lan Lung , Matthew J. Breitwisch , Simone Raoux , Chung Hon Lam
发明人： YEN-HAO SHIH , Huai-Yu Cheng , Chieh-Fang Chen , Chao-I Wu , Ming-Hsiu Lee , Hsiang-Lan Lung , Matthew J. Breitwisch , Simone Raoux , Chung Hon Lam
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： H01L45/1625 , G11C13/0004 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1641
摘要： A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions.
摘要翻译：一种具有存储元件的相变存储器件，该存储元件包括诸如硫族化物的基本相变材料和一种或多种添加剂，其中所述添加剂或添加剂沿着穿过存储元件的电极间电流路径具有非恒定浓度分布。根据不同的晶体学，热学和电学条件以及不同的相变条件，使用“非恒定”浓度分布的添加剂可以使用不同的材料和浓度掺杂不同的区域。

16. 发明申请

US20100328995A1 METHODS AND APPARATUS FOR REDUCING DEFECT BITS IN PHASE CHANGE MEMORY 有权
标题翻译：减少相变记忆中缺陷位的方法和装置
公开(公告)号：US20100328995A1
公开(公告)日：2010-12-30
申请号：US12715802
申请日：2010-03-02
申请人： YEN-HAO SHIH , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
发明人： YEN-HAO SHIH , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C29/70 , G11C2213/79
摘要： Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.
摘要翻译：相位变化存储器件和这里描述的操作方法基于以下发现：在施加到相变存储器单元以建立高电阻复位状态的初始高电流操作之后，存储器单元的电流 - 电压（IV）行为可以使用不同的偏置电压来检测存储器单元是否具有差的数据保留特性的缺陷单元。

17. 发明申请

US20100290293A1 METHOD OF IDENTIFYING LOGICAL INFORMATION IN A PROGRAMMING AND ERASING CELL BY ON-SIDE READING SCHEME 审中-公开
标题翻译：通过边界读取方案识别编程和擦除单元中的逻辑信息的方法
公开(公告)号：US20100290293A1
公开(公告)日：2010-11-18
申请号：US12845064
申请日：2010-07-28
申请人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
发明人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
IPC分类号： G11C16/04
CPC分类号： G11C16/0475
摘要： A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.
摘要翻译：公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。

18. 发明授权

US07738300B2 Memory cell and method of programming the same 有权
标题翻译：存储单元和编程方法相同
公开(公告)号：US07738300B2
公开(公告)日：2010-06-15
申请号：US12193215
申请日：2008-08-18
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C11/34
CPC分类号： G11C16/0475 , G11C16/3418 , G11C16/3427 , G11C16/3486
摘要： A method of programming a memory cell is described. The memory cell includes a gate with a charge trapping layer isolated from a substrate for storing data with a first region and a second region separated from the first region. The method of programming the memory cell includes applying a first voltage arrangement with a first gate voltage for programming the first region and applying a second voltage arrangement with a second gate voltage for programming the second region. The first gate voltage is greater than the second gate voltage.
摘要翻译：描述了对存储器单元进行编程的方法。存储单元包括具有与基板隔离的电荷捕获层的栅极，用于存储与第一区域分离的第一区域和第二区域的数据。编程存储器单元的方法包括施加具有第一栅极电压的第一电压装置，用于对第一区域进行编程，并施加具有第二栅极电压的第二电压装置，用于对第二区域进行编程。第一栅极电压大于第二栅极电压。

19. 发明申请

US20090303794A1 Structure and Method of A Field-Enhanced Charge Trapping-DRAM 审中-公开
标题翻译：场增强电荷俘获DRAM的结构和方法
公开(公告)号：US20090303794A1
公开(公告)日：2009-12-10
申请号：US12133237
申请日：2008-06-04
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C11/34 , H01L29/792 , H01L21/8247
CPC分类号： H01L27/10823 , G11C11/404 , G11C11/4076 , H01L27/10876 , H01L29/66833 , H01L29/792
摘要： A field-enhanced (FE) charge trapping-DRAM (TDRAM) device is described which is suitable for DRAM applications, and for additional applications with lower power requirements. In some embodiments, the FE-TDRAM device comprises a charge trapping FinFET structure including an upside-down U-shaped volatile programmable structure and an upside-down U-shaped dielectric structure overlying the volatile programmable structure.
摘要翻译：描述了适用于DRAM应用的场增强（FE）电荷俘获DRAM（TDRAM）器件，以及适用于具有较低功率要求的其他应用。在一些实施例中，FE-TDRAM器件包括电荷俘获FinFET结构，其包括颠倒的U形易失性可编程结构和叠置在易失性可编程结构上的倒置的U形电介质结构。

20. 发明申请

US20090103363A1 APPARATUS AND ASSOCIATED METHOD FOR MAKING A VIRTUAL GROUND ARRAY STRUCTURE THAT USES INVERSION BIT LINES 有权
标题翻译：用于制造使用反向位线的虚拟地面阵列结构的装置和相关方法
公开(公告)号：US20090103363A1
公开(公告)日：2009-04-23
申请号：US12342837
申请日：2008-12-23
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C16/06 , H01L21/8239
CPC分类号： G11C16/16 , G11C16/0466 , G11C16/12 , H01L27/0207 , H01L27/115 , H01L27/11568 , Y10S438/954
摘要： A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging.
摘要翻译：虚拟接地阵列结构使用反转位线，以消除对注入位线的需要。结果，可以减小电池尺寸，这可以提供更大的密度和更小的封装。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式