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11. 发明授权

US5783961A Inverted amplifying circuit 失效
标题翻译：反相放大电路
公开(公告)号：US5783961A
公开(公告)日：1998-07-21
申请号：US764637
申请日：1996-12-11
申请人： Changming Zhou , Guoliang Shou , Makoto Yamamoto , Sunao Takatori
发明人： Changming Zhou , Guoliang Shou , Makoto Yamamoto , Sunao Takatori
IPC分类号： H03K19/0948 , H03F1/02 , H03F1/34 , H03F3/46 , H03F3/72 , H03K5/153 , H03H11/26
CPC分类号： H03F3/72
摘要： The present invention has an object to provide an inverted amplifying circuit with improved accuracy of output and reduced electric power consumption. In an inverted amplifying circuit according to the present invention, a MOS switch is connected between pMOS and nMOS of a CMOS inverter and between balancing resistances. The MOS switch is opened when the inverted amplifying circuit does not work.
摘要翻译：本发明的目的是提供一种具有提高的输出精度和降低的电力消耗的反相放大电路。在根据本发明的反相放大电路中，MOS开关连接在CMOS反相器的pMOS和nMOS之间以及平衡电阻之间。当反相放大电路不工作时，MOS开关打开。

12. 发明授权

US6081549A Phase correction method and apparatus for spectrum spread wireless communication receiver 失效
标题翻译：频谱扩展无线通信接收机的相位校正方法及装置
公开(公告)号：US6081549A
公开(公告)日：2000-06-27
申请号：US4607
申请日：1998-01-08
申请人： Guoliang Shou , Changming Zhou , Xuping Zhou
发明人： Guoliang Shou , Changming Zhou , Xuping Zhou
IPC分类号： H04B1/707 , H04B1/712 , H04B7/01 , H04B7/08 , H04K1/00
CPC分类号： H04B1/711 , H04B7/01 , H04B1/7093 , H04B1/7117 , H04B2201/70701
摘要： Phases of the spread spectrum signal are corrected with a high degree of accuracy by a minimum of circuitry. One of phase correction circuits 31-34 of the receiver corresponds to each path. The I-component and Q-component of a despread output are supplied to the phase correction circuits 31-34. A phase error extractor 1 extracts the first phase error from a received pilot block. A phase corrector 2 corrects the phase error of a received information symbol using a correction vector that has been calculated based on the first phase error. The RAKE synthesizer 25 synthesizes the corrected received signal with outputs of the phase correction A circuits of other paths and outputs the synthesized signal to a temporary determiner 3 which temporarily determines an information symbol to be processed. The phase error is modified in a correction vector modifier 4 using the temporary determination result. A new correction vector is calculated based on the modified phase error. In this way, the correction vectors are sequentially modified based on the temporary determination results for the information symbols.
摘要翻译：通过最小的电路以高精度校正扩频信号的相位。接收机的相位校正电路31-34中的一个对应于每个路径。解扩输出的I分量和Q分量被提供给相位校正电路31-34。相位误差提取器1从接收到的导频块中提取第一相位误差。相位校正器2使用已经基于第一相位误差计算的校正矢量校正接收信息符号的相位误差。 RAKE合成器25将校正的接收信号与其他路径的相位校正A电路的输出合成，并将合成信号输出到暂时确定要处理的信息符号的临时确定器3。使用临时确定结果在校正矢量修改器4中修改相位误差。基于修正的相位误差计算新的校正矢量。以这种方式，基于信息符号的临时确定结果，顺序修改校正矢量。

13. 发明授权

US5958002A Vector absolute--value calculation circuit 失效
标题翻译：矢量绝对值计算电路
公开(公告)号：US5958002A
公开(公告)日：1999-09-28
申请号：US905784
申请日：1997-08-12
申请人： Changming Zhou , Guoliang Shou , Kunihiko Suzuki , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
发明人： Changming Zhou , Guoliang Shou , Kunihiko Suzuki , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
IPC分类号： G06G7/25 , G06G7/22 , G06G7/00 , G06G7/16
CPC分类号： G06G7/22
摘要： A highly accurate vector absolute-value calculation circuit uses analog processing and minimal hardware. Signal voltages corresponding to an I component (real number part) and a Q component (imaginary number part) are input to a first absolute-value calculation circuit 13 and a second absolute-value calculation circuit 14 through terminals 11 and 12, respectively, and they are each converted into absolute-value signals. The component I absolute-value and component Q absolute-value are compared in a comparison circuit 20. According to the result, the larger absolute-value signals are output to an input capacitor 23 of a neural computation circuit, and the smaller absolute-value signals are output to an input capacitor 24 by controlling multiplexers 21 and 22. The capacity ratio of a feedback capacitor 26 of a neural computation circuit and input capacitors 23 and 24 is 11:10:5. The complex number absolute-value calculated by the following formula is output from an output terminal 27. ##EQU1##
摘要翻译：高精度矢量绝对值计算电路采用模拟处理和最小硬件。对应于I分量（实数部分）和Q分量（虚数部分）的信号电压分别通过端子11和12输入到第一绝对值计算电路13和第二绝对值计算电路14，以及它们都被转换为绝对值信号。在比较电路20中比较分量I绝对值和分量Q绝对值。根据结果，较大的绝对值信号被输出到神经计算电路的输入电容器23，并且较小的绝对值通过控制多路复用器21和22将信号输出到输入电容器24.神经计算电路和输入电容器23和24的反馈电容器26的容量比为11:10:5。从输出端子27输出由下式计算的复数绝对值。

14. 发明授权

US5956333A Multi-user demodulator for CDMA spectrum spreading communication 失效
标题翻译：用于CDMA频谱扩展通信的多用户解调器
公开(公告)号：US5956333A
公开(公告)日：1999-09-21
申请号：US781631
申请日：1997-01-10
申请人： Changming Zhou , Guoliang Shou , Kenzo Urabe , Tetsuhiko Miyatani
发明人： Changming Zhou , Guoliang Shou , Kenzo Urabe , Tetsuhiko Miyatani
IPC分类号： H03H17/00 , H04B1/7107 , H04J13/00 , H04K1/00
CPC分类号： H04B1/71075
摘要： A multi-user demodulator eliminates synchronization problems without interference cancellation. A threshold process is applied to a despread signal to extract each user's signal. The extracted signals are respread, and those respread signals other than a specifier user's signal are subtracted from the received signal to ideally extract the specific user's signal.
摘要翻译：多用户解调器消除了无干扰消除的同步问题。对解扩信号应用阈值处理以提取每个用户的信号。提取的信号被重新发送，并且从接收到的信号中减去除指定者用户信号之外的那些再现信号，以理想地提取特定用户的信号。

15. 发明授权

US5930157A Autocorrelation coefficient operator having analog circuit element 失效
标题翻译：具有模拟电路元件的自相关系数算子
公开(公告)号：US5930157A
公开(公告)日：1999-07-27
申请号：US895272
申请日：1997-07-16
申请人： Ichiro Matsumoto , Changming Zhou , Guoliang Shou
发明人： Ichiro Matsumoto , Changming Zhou , Guoliang Shou
IPC分类号： G06F17/10 , G06F17/15 , G06J1/00 , G06F7/12
CPC分类号： G06J1/00
摘要： The autocorrelation coefficient operator 60 carries out an integration operation to determine the autocorrelation coefficient for audio signal processing or other types of signal processing at high speed with low power consumption. The input signal S is digitized in the A/D converter 30 to the digital signal SP and supplied to a delay unit 40, which delays and holds the digital signal SP sequentially. A sample holder 45 also samples and holds the analog signal S in synchronization with the delay unit 40. When the number of sampled values held by the sample holder 45 reaches a predetermined value, the sample holder 45 outputs the sampled values at the same time in accordance with a sampling clock signal CK which is supplied by a clock signal generator 35. Delayed values held in the delay unit 40 are shifted and output sequentially in accordance with a shift clock signal SCK, the frequency of which is higher than that of the sampling clock signal CK. A weighted addition circuit 50 integrates these sampled values and the delayed values to calculate the autocorrelation coefficient R.
摘要翻译：自相关系数运算器60执行积分运算，以低功耗确定音频信号处理的自相关系数或其他类型的信号处理。输入信号S在A / D转换器30中数字化为数字信号SP，并提供给延迟单元40，延迟单元40依次延迟和保持数字信号SP。样本保持器45还与延迟单元40同步地采样并保持模拟信号S.当采样保持器45保持的采样值的数量达到预定值时，样本保持器45同时输出采样值根据由时钟信号发生器35提供的采样时钟信号CK。保持在延迟单元40中的延迟值根据频率高于采样的移位时钟信号SCK被顺序移位和输出时钟信号CK。加权加法电路50对这些采样值和延迟值进行积分，以计算自相关系数R.

16. 发明授权

US5815812A Soft handoff system of spread spectrum communication 失效
标题翻译：软切换系统的扩频通信
公开(公告)号：US5815812A
公开(公告)日：1998-09-29
申请号：US760257
申请日：1996-12-05
申请人： Changming Zhou , Guoliang Shou , Makoto Yamamoto , Mamoru Sawahashi , Fumiyuki Adachi , Sunao Takatori
发明人： Changming Zhou , Guoliang Shou , Makoto Yamamoto , Mamoru Sawahashi , Fumiyuki Adachi , Sunao Takatori
IPC分类号： H04J13/00 , H04B1/7093 , H04W36/18 , H04W36/36 , H04Q7/32
CPC分类号： H04B1/7093 , H04W36/18
摘要： The present invention provides a system for soft handoff, which processes in high speed. A system according to the present invention substantially realizes a multiplication by a circuit for classifying received signals from a plurality of cell site stations once held in an analog sampling and holding circuit into two groups, multiplication and accumulation, by a small circuit of low electric power consumption.
摘要翻译：本发明提供了一种用于软切换的系统，其高速处理。根据本发明的系统基本上实现了一种电路的乘法，该电路用于将一次保持在模拟采样和保持电路中的多个小区站点的接收信号分类成两组，通过低功率的小电路进行乘法和累加消费。

17. 发明授权

US5815021A Weight addition circuit 失效
标题翻译：加权电路
公开(公告)号：US5815021A
公开(公告)日：1998-09-29
申请号：US686761
申请日：1996-07-26
申请人： Guoliang Shou , Changming Zhou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Changming Zhou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
IPC分类号： G06G7/14 , G06J1/00 , G06G7/16
CPC分类号： G06J1/00 , G06G7/14
摘要： The present invention provides a weighted addition circuit for sampling, holding and performing weighted addition by a circuit smaller than a conventional one. In the weighted addition circuit of to the present invention, a capacitive coupling is connected to a plurality of switches which are further connected only to an input voltage. A voltage is held and a weight is added in the capacitive coupling.
摘要翻译：本发明提供一种加权加法电路，用于通过比传统电路小的电路进行采样，保持和执行加权相加。在本发明的加权加法电路中，电容耦合连接到多个开关，该开关进一步仅与输入电压相连。在电容耦合中保持电压并加上重量。

18. 发明授权

US06563373B1 Filter circuit utilizing a plurality of sampling and holding circuits 有权
标题翻译：利用多个取样和保持电路的滤波电路
公开(公告)号：US06563373B1
公开(公告)日：2003-05-13
申请号：US09165301
申请日：1998-10-02
申请人： Guoliang Shou , Kunihiko Suzuki , Changming Zhou
发明人： Guoliang Shou , Kunihiko Suzuki , Changming Zhou
IPC分类号： H03H1502
CPC分类号： H04B1/7093 , H03H11/04
摘要： An analog calculation circuit in a filter circuit is corrected in the calculation error by estimating the error from a calculation result of known inputs and known multiplier. A multiplier is changed according to the estimated error. The filter circuit has a voltage to current converter at an input side and a current to voltage converter at an output side and a calculation of current is performed therein.
摘要翻译：滤波器电路中的模拟计算电路通过从已知输入和已知乘数的计算结果估计误差来校正计算误差。根据估计的误差改变乘数。滤波电路在输入侧具有电压 - 电流转换器，在输出侧具有电流 - 电压转换器，并且在其中执行电流计算。

19. 发明授权

US6038250A Initial synchronization method and receiver for DS-CDMA inter base station asynchronous cellular system 失效
标题翻译：用于DS-CDMA基站间异步蜂窝系统的初始同步方法和接收机
公开(公告)号：US6038250A
公开(公告)日：2000-03-14
申请号：US3509
申请日：1998-01-06
申请人： Guoliang Shou , Changming Zhou , Xuping Zhou
发明人： Guoliang Shou , Changming Zhou , Xuping Zhou
IPC分类号： H04B1/707 , H04B1/7075 , H04B7/26 , H04W56/00 , H04W76/02 , H04B7/216
CPC分类号： H04B1/7077 , H04B1/7083 , H04B1/70735 , H04B1/70751 , H04B2201/70702
摘要： Cells are searched at a high speed using an initial synchronization method and a receiver for a DS-CDMA inter base station asynchronous cellular system. A base band received signal is input to a matched filter and is correlated with a spread code supplied from a spread code generator. A signal electric power calculator calculates the electric power of the correlation output of the matched filter, and outputs the result to a long code synchronization timing determiner, a threshold value calculator, and a long code identifier. During the initial cell search, the spread code generator outputs a short code #0 that is common to the control channel of each of the base stations. After the long code synchronization timing has been determined, each of the segments of the N chips which constitutes a portion of the synthesized spread code sequence synthesized from a long code #i that is unique to each of the base stations and the short code #0 is sequentially replaced and output.
摘要翻译：使用初始同步方法和用于DS-CDMA基站间异步蜂窝系统的接收机以高速搜索小区。基带接收信号被输入到匹配滤波器，并与从扩展码发生器提供的扩展码相关。信号电力计算器计算匹配滤波器的相关输出的功率，并将结果输出到长码同步定时确定器，阈值计算器和长码标识符。在初始小区搜索期间，扩频码发生器输出每个基站的控制信道共同的短码＃0。在确定了长代码同步定时之后，构成从每个基站唯一的长码#i合成的合成扩展码序列的一部分的N个码片的每个片段和短码＃0 顺序更换并输出。

20. 发明授权

US5959875A Analog signal characterizer for functional transformation 失效
标题翻译：用于功能转换的模拟信号表征器
公开(公告)号：US5959875A
公开(公告)日：1999-09-28
申请号：US812650
申请日：1997-03-07
申请人： Nobuaki Kawahara , Kenzo Urabe , Changming Zhou , Guoliang Shou
发明人： Nobuaki Kawahara , Kenzo Urabe , Changming Zhou , Guoliang Shou
IPC分类号： G06G7/19
CPC分类号： G06G7/1921
摘要： A signal characterizer for performing functional transformations such as Fast Fourier Transforms (FFTs), which converts an input serial analog signal into a plurality of parallel discrete signals using an analog-type serial-to-parallel converter. The discrete signals are then supplied to the input terminals of butterfly operation circuits to process the parallel discrete signals into a plurality of transformed signals. A switch supplies the transformed signals to a serial signal output terminal. The switch is controlled by a controller so that the input signal sequence is converted to a serial signal sequence according to a predetermined order.
摘要翻译：一种用于执行诸如快速傅立叶变换（FFT）的功能变换的信号表征器，其使用模拟型串并转换器将输入的串行模拟信号转换为多个并行离散信号。然后将离散信号提供给蝶形运算电路的输入端，以将并行离散信号处理成多个变换信号。开关将变换的信号提供给串行信号输出端子。开关由控制器控制，使得输入信号序列根据预定顺序被转换成串行信号序列。

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