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11. 发明授权

US08667049B2 Massively parallel supercomputer 有权
标题翻译：大容量并行超级计算机
公开(公告)号：US08667049B2
公开(公告)日：2014-03-04
申请号：US13566024
申请日：2012-08-03
申请人： Matthias A. Blumrich , Dong Chen , George L. Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampap , Philip Heidlberger , Gerard V. Kopcsay , Lawrence S. Mok , Todd E. Takken
发明人： Matthias A. Blumrich , Dong Chen , George L. Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampap , Philip Heidlberger , Gerard V. Kopcsay , Lawrence S. Mok , Todd E. Takken
IPC分类号： G06F15/173
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. The multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions.
摘要翻译：数百个teraOPS级别的新型大规模并行超级计算机包括基于片上系统技术的节点架构，即每个处理节点包括单个专用集成电路（ASIC）。在每个ASIC节点内是多个处理元件，每个处理元件由中央处理单元（CPU）和多个浮点处理器组成，以实现计算性能，封装密度，低成本以及功率和冷却要求的最佳平衡。单个节点内的多个处理器单独或同时工作在要解决的特定算法所要求的计算或通信的任何组合上。片上系统ASIC节点通过多个独立网络互连，从而最大限度地最大限度地提高了分组通信吞吐量并最大限度地减少了延迟。多个网络包括用于并行算法消息传递的三个高速网络，包括Torus，全局树和提供全局障碍和通知功能的全球异步网络。

12. 发明授权

US5343366A Packages for stacked integrated circuit chip cubes 失效
标题翻译：堆叠集成电路芯片立方体的封装
公开(公告)号：US5343366A
公开(公告)日：1994-08-30
申请号：US903838
申请日：1992-06-24
申请人： Thomas M. Cipolla , Paul W. Coteus , Ioannis Damianakis , Glen W. Johnson , Peter G. Ledermann , Linda C. Matthew , Lawrence S. Mok
发明人： Thomas M. Cipolla , Paul W. Coteus , Ioannis Damianakis , Glen W. Johnson , Peter G. Ledermann , Linda C. Matthew , Lawrence S. Mok
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07 , H05K1/14 , H05K1/18 , H05K3/32 , H05K3/34 , H05K3/36 , H05K3/40 , H01R23/68
CPC分类号： H05K3/363 , H01L24/01 , H01L25/0652 , H01L25/0657 , H01L2225/06551 , H01L2225/06596 , H01L2924/09701 , H01L2924/14 , H01L2924/3011 , H05K2201/0397 , H05K2201/048 , H05K2201/09172 , H05K2201/09909 , H05K2201/10484 , H05K2201/1059 , H05K2201/10681 , H05K2201/10984 , H05K3/326 , H05K3/3452 , H05K3/3457 , H05K3/366 , H05K3/4007 , H05K3/4092
摘要： This invention relates to three dimensional packaging of integrated circuit chips into stacks to form cuboid structures. Between adjacent chips in the stack, there is disposed an electrical interconnection means which is a first substrate having a plurality of conductors one end of which is electrically connected to chip contact locations and the other end of which extends to one side of the chip stack to form a plurality of pin-like electrical interconnection assemblies. The pin-like structures can be formed from projections of the first substrate having an electrical conductor on at least one side thereof extending from this side. Alternatively, the pin-like structures can be formed from conductors which cantilever from both sides of an edge of the first substrate and within which corresponding conductors from both sides are aligned and spaced apart by the first substrate thickness. The spaces contain solder and form solder loaded pin-like structures. The pin-like structures can be directly solder bonded to conductors on a second substrate surface or the pin-like structures can be adapted for insertion into apertures in a second substrate. The second substrate provides a means for electrically inter-connecting a plurality of these cuboids. Preferably, the first and second substrates are circuitized flexible polymeric films. The second substrate is disposed on a third substrate, such as a PC board, with a resilient material therebetween which permits a heat sink to be pressed into intimate contact with an opposite side of the cuboid structures.
摘要翻译：本发明涉及将集成电路芯片三维封装成堆栈以形成立方体结构。在堆叠中的相邻芯片之间，设置有电互连装置，其是具有多个导体的第一基板，其多个导体电连接到芯片接触位置，并且其另一端延伸到芯片堆叠的一侧，形成多个针状电互连组件。销状结构可以由在其至少一侧上具有电导体的第一基板的凸起从该侧延伸形成。或者，销状结构可以由从第一基板的边缘的两侧悬臂的导体形成，并且其中来自两侧的相应导体对准并且间隔开第一基板厚度。这些空间包含焊料并形成焊料加载的针状结构。销状结构可以直接焊接到第二衬底表面上的导体上，或者针状结构可以适于插入到第二衬底中的孔中。第二基板提供用于电连接多个这些长方体的装置。优选地，第一和第二基底是电路化柔性聚合物膜。第二基板设置在诸如PC板的第三基板上，其间具有弹性材料，其允许将散热器压紧成与长方体结构的相对侧紧密接触。

13. 发明申请

US20090259713A1 NOVEL MASSIVELY PARALLEL SUPERCOMPUTER 有权
标题翻译：新的大型并行超级计算机
公开(公告)号：US20090259713A1
公开(公告)日：2009-10-15
申请号：US12492799
申请日：2009-06-26
申请人： Matthias A. Blumrich , Dong Chen , George L. Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Gerard V. Kopcsay , Lawrence S. Mok , Todd E. Takken
发明人： Matthias A. Blumrich , Dong Chen , George L. Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Gerard V. Kopcsay , Lawrence S. Mok , Todd E. Takken
IPC分类号： G06F15/76 , G06F15/16 , G06F11/28 , G06F12/08 , G06F9/02 , G06F15/177
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input/Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.
摘要翻译：数百个teraOPS级别的新型大规模并行超级计算机包括基于片上系统技术的节点架构，即每个处理节点包括单个专用集成电路（ASIC）。在每个ASIC节点内是多个处理元件，每个处理元件由中央处理单元（CPU）和多个浮点处理器组成，以实现计算性能，封装密度，低成本以及功率和冷却要求的最佳平衡。单个节点内的多个处理器可以单独使用或同时使用，以在任何时间点解决或执行的特定算法所要求的任何计算或通信组合上工作。片上系统ASIC节点通过多个独立网络互连，从而最大限度地最大限度地提高了分组通信吞吐量并最大限度地减少了延迟。在优选实施例中，多个网络包括用于并行算法消息传递的三个高速网络，包括提供全局障碍和通知功能的环形，全局树和全球异步网络。这些多个独立网络可以根据用于优化算法处理性能的算法的需求或阶段来协同或独立地利用。对于特定类别的并行算法或并行计算的部分，该架构具有出色的计算性能，并且可以启用对新类并行算法执行计算。为外部连接提供附加网络，用于输入/输出，系统管理和配置以及调试和监控功能。实现中平面和其他硬件设备的特殊节点打包技术有助于在多个网络中划分超级计算机，以优化超级计算资源。

14. 发明申请

US20080002357A1 Thermal docking fansink 有权
标题翻译：散热器散热器
公开(公告)号：US20080002357A1
公开(公告)日：2008-01-03
申请号：US11480292
申请日：2006-06-30
申请人： Albert V. Makley , Thomas M. Cipolla , Thomas R. Hildner , Vinod Kamath , Fumitoshi Kiyooka , Lawrence S. Mok , Fusanobu Nakamura
发明人： Albert V. Makley , Thomas M. Cipolla , Thomas R. Hildner , Vinod Kamath , Fumitoshi Kiyooka , Lawrence S. Mok , Fusanobu Nakamura
IPC分类号： G06F1/20
CPC分类号： G06F1/203
摘要： A fansink arrangement for a laptop computer wherein two distinct patterns of air intake can be employed. Particularly, dual air intakes of the laptop can be managed and controlled depending upon an operating mode of the computer. Thus, when the computer is in a “stand alone” mode, only one air intake is employed while in a “docking” mode of the computer two air intakes are employed.
摘要翻译：一种用于膝上型计算机的风扇排列装置，其中可以采用两种截然不同的进气模式。特别地，可以根据计算机的操作模式来管理和控制膝上型计算机的双重进气口。因此，当计算机处于“独立”模式时，在计算机的“对接”模式中仅采用一个进气口，两个进气口被采用。

15. 发明授权

US06791836B2 Smart fan modules and system 有权
标题翻译：智能风扇模块和系统
公开(公告)号：US06791836B2
公开(公告)日：2004-09-14
申请号：US10437766
申请日：2003-05-14
申请人： Thomas M. Cipolla , Richard I. Kaufman , Lawrence S. Mok
发明人： Thomas M. Cipolla , Richard I. Kaufman , Lawrence S. Mok
IPC分类号： G06F120
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A fan module including: two or more individual fans, each fan having an air movement means and a motor engaged with the air movement means for accelerating air entering each of the two or more individual fans; a temperature sensor for sensing a temperature associated with the two or more fans and for outputting a first signal corresponding to the temperature; rotational speed sensor for outputting a second signal corresponding to a rotational speed of each of the two or more fans; and a processor for receiving the first and second signals and controlling the two or more individual fans based on the first and second signals.
摘要翻译：一种风扇模块，包括：两个或多个独立的风扇，每个风扇具有空气运动装置和与空气运动装置接合的马达，用于加速进入两个或更多个独立风扇中的每一个的空气; 温度传感器，用于感测与两个或更多个风扇相关联的温度，并输出对应于该温度的第一信号; 转速传感器，用于输出与所述两个或更多个风扇中的每一个的旋转速度对应的第二信号; 以及处理器，用于接收第一和第二信号，并且基于第一和第二信号来控制两个或多个单独的风扇。

16. 发明授权

US07761687B2 Ultrascalable petaflop parallel supercomputer 失效
标题翻译：超平面petaflop平行超级计算机
公开(公告)号：US07761687B2
公开(公告)日：2010-07-20
申请号：US11768905
申请日：2007-06-26
申请人： Matthias A. Blumrich , Dong Chen , George Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Shawn Hall , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Martin Ohmacht , Valentina Salapura , Krishnan Sugavanam , Todd Takken
发明人： Matthias A. Blumrich , Dong Chen , George Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Shawn Hall , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Martin Ohmacht , Valentina Salapura , Krishnan Sugavanam , Todd Takken
IPC分类号： G06F15/173
CPC分类号： G06F15/17337
摘要： A massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. The use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.
摘要翻译： petaOPS规模的大规模并行超级计算机包括基于片上系统技术的节点架构，其中每个处理节点包括具有多达四个处理元件的单个专用集成电路（ASIC）。 ASIC节点通过多个独立网络互连，以最小的延迟最大化节点之间的数据包通信的吞吐量。多个网络可以包括用于并行算法消息传递的三个高速网络，包括Torus，集合网络和提供全局障碍和通知功能的全球异步网络。这些多个独立网络可以根据用于优化算法处理性能的算法的需求或阶段来协同或独立地利用。提供DMA引擎的使用以促进节点之间的消息传递，而不需要节点处理资源。

17. 发明申请

US20080026627A1 PIN GRID ARRAY ZERO INSERTION FORCE CONNECTORS CONFIGURABLE FOR SUPPORTING LARGE PIN COUNTS 有权
标题翻译： PIN网格阵列插入力连接器可配置为支持大量PIN码
公开(公告)号：US20080026627A1
公开(公告)日：2008-01-31
申请号：US11496153
申请日：2006-07-31
申请人： Gareth Geoffrey Hougham , William Louis Brodsky , Thomas M. Cipolla , Paul William Coteus , Ronald Malfatt
发明人： Gareth Geoffrey Hougham , William Louis Brodsky , Thomas M. Cipolla , Paul William Coteus , Ronald Malfatt
IPC分类号： H01R4/50
CPC分类号： H01R13/193 , H05K7/1007
摘要： A PGA socket including a plurality of sub-socket components, which when used in combination forms a larger effective socket, includes multiple apertures configured to receive corresponding pins of an IC. The PGA socket further includes multiple contact members, each of the contact members corresponding to a respective one of the apertures. The contact members are configured to movably engage corresponding pins of the IC upon respective movement of the apertures so as to provide electrical and mechanical contact thereto. Each of the sub-socket components is configured to mechanically engage at least one of the other sub-socket components such that the contact members in each of the sub-socket components are capable of electrically connecting to corresponding pins of the IC substantially simultaneously.
摘要翻译：包括多个子插座部件的PGA插座，当组合使用时形成较大的有效插座，包括配置成接收IC的相应引脚的多个孔。 PGA插座还包括多个接触构件，每个接触构件对应于相应的一个孔。接触构件被构造成在孔的相应移动时可移动地接合IC的相应销，以便提供与其的电和机械接触。每个子插座部件被构造成机械地接合其他子插座部件中的至少一个，使得每个子插座部件中的接触部件能够基本上同时电连接到IC的相应引脚。

18. 发明授权

US4875614A Alignment device 失效
标题翻译：对准装置
公开(公告)号：US4875614A
公开(公告)日：1989-10-24
申请号：US264713
申请日：1988-10-31
申请人： Thomas M. Cipolla , Raymond R. Horton , Philip Murphy , Michael J. Palmer
发明人： Thomas M. Cipolla , Raymond R. Horton , Philip Murphy , Michael J. Palmer
IPC分类号： H01L21/60 , B23K20/02 , F16C19/50 , H01L21/00
CPC分类号： F16C19/50 , B23K20/02 , H01L21/67144 , H01L24/78 , H01L2224/75745 , H01L2224/75823 , H01L2224/78 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01082 , Y10S269/903
摘要： Apparatus for automatically adjusting the orientation of a first surface of a first body to be against a second surface of a second body when said first surface is pressed against said second surface. The apparatus includes a means for movably mounting the first body to a support which permits rotation of the first surface so that when the first surface is pressed against the second surface, the first surface rotates with respect to the support resulting in the first surface being against the second surface.

19. 发明授权

US4349277A Non-contact measurement of surface profile 失效
标题翻译：非接触式测量表面轮廓
公开(公告)号：US4349277A
公开(公告)日：1982-09-14
申请号：US158372
申请日：1980-06-11
申请人： Joseph L. Mundy , Gilbert B. Porter, III , Thomas M. Cipolla
发明人： Joseph L. Mundy , Gilbert B. Porter, III , Thomas M. Cipolla
IPC分类号： G01B11/24 , G01B11/25 , G01B11/30 , G01B11/00 , G01C3/20
CPC分类号： G01B11/2509
摘要： A parallax method of wavelength labeling is based on optical triangulation. A complementary color pattern projected onto the surface is characterized by a continuous variation of the power ratio of two wavelength bands, and the profile can be measured at all points in the field of view. Shifts of the wavelength bands on separate detector arrays correspond to profile deviations. A signal processor calculates a normalized signal that is independent of surface reflectivity and roughness variations; the phase shift of this signal yields depth data from which the surface profile can be mapped.
摘要翻译：波长标注的视差法基于光学三角测量。投影到表面上的互补色图案的特征在于两个波段的功率比的连续变化，并且可以在视场中的所有点处测量轮廓。分离的检测器阵列上的波段的移位对应于轮廓偏差。信号处理器计算独立于表面反射率和粗糙度变化的归一化信号; 该信号的相移产生可以映射表面轮廓的深度数据。

20. 发明授权

US08081473B2 Apparatus and method of direct water cooling several parallel circuit cards each containing several chip packages 失效
标题翻译：直接水冷几种并行电路卡的装置和方法，每个包含几个芯片封装
公开(公告)号：US08081473B2
公开(公告)日：2011-12-20
申请号：US12185520
申请日：2008-08-04
申请人： Thomas M. Cipolla , Evan George Colgan , Paul W. Coteus , Shawn Anthony Hall , Shurong Tian
发明人： Thomas M. Cipolla , Evan George Colgan , Paul W. Coteus , Shawn Anthony Hall , Shurong Tian
IPC分类号： H05K5/00 , H05K7/20 , G06F1/20 , F28D15/00 , H01L23/495
CPC分类号： H01L23/473 , F28D15/00 , F28D15/02 , H01L23/4093 , H01L2924/0002 , H01L2924/00
摘要： A cooling apparatus, system and like method for an electronic device includes a plurality of heat producing electronic devices affixed to a wiring substrate. A plurality of heat transfer assemblies each include heat spreaders and thermally communicate with the heat producing electronic devices for transferring heat from the heat producing electronic devices to the heat transfer assemblies. The plurality of heat producing electronic devices and respective heat transfer assemblies are positioned on the wiring substrate having the regions overlapping. A heat conduit thermally communicates with the heat transfer assemblies. The heat conduit circulates thermally conductive fluid therethrough in a closed loop for transferring heat to the fluid from the heat transfer assemblies via the heat spreader. A thermally conductive support structure supports the heat conduit and thermally communicates with the heat transfer assemblies via the heat spreader transferring heat to the fluid of the heat conduit from the support structure.
摘要翻译：电子设备的冷却装置，系统等方法包括固定在布线基板上的多个发热电子器件。多个传热组件各自包括散热器，并与制热电子设备热连通，用于将热量从发热电子设备传递到传热组件。多个发热电子器件和各个传热组件位于具有重叠区域的布线基板上。热导管与传热组件热连通。热导管将导热流体循环通过其中的闭环，用于通过散热器将热量传递给来自传热组件的流体。导热支撑结构支撑热导管，并且通过散热器与传热组件热连通，散热器将热量从支撑结构传递到热导管的流体。

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