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11. 发明申请

US20090079747A1 Distributed Antialiasing In A Multiprocessor Graphics System 有权
标题翻译：多处理器图形系统中的分布式抗锯齿
公开(公告)号：US20090079747A1
公开(公告)日：2009-03-26
申请号：US11383048
申请日：2006-05-12
申请人： Philip Browning Johnson , Brian M. Kelleher , Franck R. Diard
发明人： Philip Browning Johnson , Brian M. Kelleher , Franck R. Diard
IPC分类号： G06T1/20
CPC分类号： G06T15/503 , G06T2200/28 , G06T2210/52
摘要： Multiprocessor graphics systems support distributed antialiasing. In one embodiment, two (or more) graphics processors each render a version of the same image, with a difference in the sampling location (or locations) used for each pixel. A display head combines corresponding pixels generated by different graphics processors to produce an antialiased image. This distributed antialiasing technique can be scaled to any number of graphics processors.
摘要翻译：多处理器图形系统支持分布式抗锯齿。在一个实施例中，两个（或多个）图形处理器各自呈现相同图像的版本，其中每个像素使用的采样位置（或位置）有差异。显示头组合由不同图形处理器生成的相应像素以产生抗锯齿图像。这种分布式抗锯齿技术可以扩展到任何数量的图形处理器。

12. 发明授权

US6088043A Scalable graphics processor architecture 失效
标题翻译：可扩展的图形处理器架构
公开(公告)号：US6088043A
公开(公告)日：2000-07-11
申请号：US70162
申请日：1998-04-30
申请人： Brian M. Kelleher , Thomas E. Dewey
发明人： Brian M. Kelleher , Thomas E. Dewey
IPC分类号： G06T15/00 , G06F15/16
CPC分类号： G06T15/005
摘要： A scalable graphics processor architecture is disclosed in accordance with the present invention. In a first aspect, the architecture comprises a base graphics architecture. The architecture further includes an expansion graphic architecture, the expansion graphics architecture being mateably coupled to the base graphics architecture. In a second aspect, the architecture comprises a plurality of rendering processors, a first bus coupled to the plurality of processors for providing I/O signals to the processors; and a plurality of digital to analog converters (VDACs). In this aspect, each of the VDACs are adapted for driving a display. The architecture further includes a second bus coupled between the plurality of rendering processors and the plurality of VDACs for providing image data therebetween; and a switch, coupled to a plurality of processors. The switch selectively drives the rendering processors such that one of the plurality of the VDACs are driven by all of the rendering processors when the switch is in a first mode and the rendering processors drive all of the plurality of VDACs when the switch is in a second mode. Through the use of this architecture, the graphics processor system is expandable to allow more rendering processors to be added as well as allowing the processors to drive multiple VDACs or drive a single VDAC together.
摘要翻译：根据本发明公开了一种可扩展的图形处理器架构。在第一方面，该架构包括基本图形架构。该架构还包括扩展图形架构，扩展图形架构可以适配地耦合到基本图形架构。在第二方面，该架构包括多个渲染处理器，第一总线耦合到多个处理器，用于向处理器提供I / O信号; 和多个数模转换器（VDAC）。在这方面，每个VDAC适于驱动显示器。该架构还包括耦合在多个渲染处理器和多个VDAC之间的第二总线，用于在它们之间提供图像数据; 以及耦合到多个处理器的开关。所述开关选择性地驱动所述渲染处理器，使得当所述切换器处于第一模式时，所述多个所述VDAC中的一个由所述渲染处理器驱动，并且所述渲染处理器在所述切换器处于第二模式时驱动所述多个VDAC 模式。通过使用此架构，图形处理器系统可扩展以允许添加更多渲染处理器，并允许处理器驱动多个VDAC或一起驱动单个VDAC。

13. 发明授权

US5218678A System and method for atomic access to an input/output device with direct memory access 失效
标题翻译：用于原子访问具有直接存储器访问的输入/输出设备的系统和方法
公开(公告)号：US5218678A
公开(公告)日：1993-06-08
申请号：US440588
申请日：1989-11-17
申请人： Brian M. Kelleher , Shu-Shia Chow
发明人： Brian M. Kelleher , Shu-Shia Chow
IPC分类号： G06F13/12 , G06F3/14 , G06F15/167
CPC分类号： G06F15/167 , G06F3/14
摘要： A system (30) for atomic access to an I/O device with DMA includes a CPU (32) connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is connected by a system bus (38) to a random access memory (RAM) (40), a cache (42) and an interface (44) in graphics subsystem (45). The interface (44) is connected by bus (46) to graphics processor (48). In this system, graphics subsystem (45) is an I/O device, and atomic access to it is required. Command packet interface (44) to the graphics subsystem (45) transfers geometry and graphics context information from main memory (40) to the graphics subsystem (45). For such transfers, an application writes a list of commands to a physically contiguous locked-down memory buffer (47) in its own address space. Since the system (30) has DMA, the buffer (47) resides in the main memory system (40). When the buffer (47) is full, the CPU (32) tells the graphics subsystem (45), via a read from an I/O address on the graphics subsystem (45), that it should begin a transfer of the command packet. Status of the operation is returned as a result of the I/O read transaction. After initiating the command packet transfer, the graphics subsystem (45) parses the packet and executes the appropriate operations atomically.

14. 发明授权

US08427496B1 Method and system for implementing compression across a graphics bus interconnect 有权
标题翻译：用于在图形总线互连上实现压缩的方法和系统
公开(公告)号：US08427496B1
公开(公告)日：2013-04-23
申请号：US11129099
申请日：2005-05-13
申请人： Anthony Michael Tamasi , John M. Danskin , David G. Reed , Brian M. Kelleher
发明人： Anthony Michael Tamasi , John M. Danskin , David G. Reed , Brian M. Kelleher
IPC分类号： G06F12/02 , G06T9/00 , G06T1/60
CPC分类号： G06F12/02 , G06T1/60 , G06T9/00 , H04N19/428
摘要： A system for compressed data transfer across a graphics bus in a computer system. The system includes a bridge, a system memory coupled to the bridge, and a graphics bus coupled to the bridge. A graphics processor is coupled to the graphics bus. The graphics processor is configured to compress graphics data and transfer compressed graphics data across the graphics bus to the bridge for subsequent storage in the system memory.
摘要翻译：用于在计算机系统中跨图形总线进行压缩数据传输的系统。该系统包括桥接器，耦合到桥接器的系统存储器以及耦合到桥接器的图形总线。图形处理器耦合到图形总线。图形处理器被配置为压缩图形数据并将图形总线上的压缩图形数据传送到桥接器，用于后续存储在系统存储器中。

15. 发明授权

US08130227B2 Distributed antialiasing in a multiprocessor graphics system 有权
标题翻译：多处理器图形系统中的分布式抗混叠
公开(公告)号：US08130227B2
公开(公告)日：2012-03-06
申请号：US11383048
申请日：2006-05-12
申请人： Philip Browning Johnson , Brian M. Kelleher , Franck R. Diard
发明人： Philip Browning Johnson , Brian M. Kelleher , Franck R. Diard
IPC分类号： G06T15/00 , G09G5/00 , G06F15/16
CPC分类号： G06T15/503 , G06T2200/28 , G06T2210/52
摘要： Multiprocessor graphics systems support distributed antialiasing. In one embodiment, two (or more) graphics processors each render a version of the same image, with a difference in the sampling location (or locations) used for each pixel. A display head combines corresponding pixels generated by different graphics processors to produce an antialiased image. This distributed antialiasing technique can be scaled to any number of graphics processors.
摘要翻译：多处理器图形系统支持分布式抗锯齿。在一个实施例中，两个（或多个）图形处理器各自呈现相同图像的版本，其中每个像素使用的采样位置（或位置）有差异。显示头组合由不同图形处理器生成的相应像素以产生抗锯齿图像。这种分布式抗锯齿技术可以扩展到任意数量的图形处理器。

16. 发明授权

US5287438A System and method for drawing antialiased polygons 失效
标题翻译：绘制抗锯齿多边形的系统和方法
公开(公告)号：US5287438A
公开(公告)日：1994-02-15
申请号：US929845
申请日：1992-08-13
申请人： Brian M. Kelleher
发明人： Brian M. Kelleher
IPC分类号： G06T11/20 , G06T11/40 , G06T15/50 , G06F3/14
CPC分类号： G06T11/40 , G06T15/503
摘要： A system (30) draws antialiased polygons. A CPU (32) is connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is connected by a 32-bit system bus (38) to a random access memory (RAM) (40), a cache (42) and an interface (44) in graphics subsystem (45). The interface (44) is connected by bus (46) to graphics processor (48). The graphics processor (48) is connected by 120-bit graphics bus (50) to frame buffer (52). The frame buffer (52) is connected to a video digital to analog converter (DAC) (54) by bus (56). The DAC (54) is connected to video display (58) by line (60). The graphics processor (48) use a technique known as super-sampling to combat the effects of aliasing. In aliased mode, the graphics processor (48) use 16 array sites to sample 16 pixels (72). When drawing a polygon or line in antialiased mode, the graphics processor (48) uses the 16 sites to sample at 16 locations (120) within a single pixel (72). The antialiasing is done by determining what proportion of the locations (120) within each pixel (72) are within the polygon and setting a color of each pixel (72) on the basis of the proportion.
摘要翻译：系统（30）绘制抗锯齿多边形。总线（36）将CPU（32）连接到浮点处理器（FPU）（34）。 CPU（32）通过32位系统总线（38）连接到图形子系统（45）中的随机存取存储器（RAM）（40），高速缓冲存储器（42）和接口（44）。接口（44）通过总线（46）连接到图形处理器（48）。图形处理器（48）通过120位图形总线（50）连接到帧缓冲器（52）。帧缓冲器（52）通过总线（56）连接到视频数模转换器（DAC）（54）。 DAC（54）通过线（60）连接到视频显示器（58）。图形处理器（48）使用称为超采样的技术来抵抗混叠的影响。在混叠模式下，图形处理器（48）使用16个阵列位点来采样16像素（72）。当以抗锯齿模式绘制多边形或线时，图形处理器（48）使用16个位点在单个像素（72）内的16个位置（120）进行采样。通过确定每个像素（72）内的位置（120）在多边形内的比例以及根据比例设置每个像素（72）的颜色来完成抗锯齿。

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