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11. 发明授权

US07666727B2 Semiconductor device having a laterally modulated gate workfunction and method of fabrication 失效
标题翻译：具有横向调制的栅极功能函数和制造方法的半导体器件
公开(公告)号：US07666727B2
公开(公告)日：2010-02-23
申请号：US11099190
申请日：2005-04-04
申请人： Brian Doyle , Scott A. Hareland , Mark Doczy , Robert S. Chau
发明人： Brian Doyle , Scott A. Hareland , Mark Doczy , Robert S. Chau
IPC分类号： H01L21/336 , H01L21/4763
CPC分类号： H01L29/4983 , H01L21/28079 , H01L21/28088 , H01L21/28105 , H01L21/28194 , H01L21/28202 , H01L21/32051 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659
摘要： A transistor comprising a gate electrode formed on a gate dielectric layer formed on a substrate. A pair of source/drain regions are formed in the substrate on opposite sides of the laterally opposite sidewalls of the gate electrode. The gate electrode has a central portion formed on the gate dielectric layer and over the substrate region between the source and drain regions and a pair sidewall portions which overlap a portion of the source/drain regions wherein the central portion has a first work function and said pair of sidewall portions has a second work function, wherein the second work function is different than the first work function.
摘要翻译：一种晶体管，包括形成在形成于基板上的栅介质层上的栅电极。在栅电极的横向相对的侧壁的相对侧上的衬底中形成一对源极/漏极区域。栅极电极具有形成在栅极介电层上并且在源极和漏极区域之间的衬底区域上的中心部分和与源极/漏极区域的一部分重叠的一对侧壁部分，其中中心部分具有第一功函数和所述一对侧壁部分具有第二功函数，其中第二功函数不同于第一功函数。

12. 发明授权

US07435637B2 Quantum wire gate device and method of making same 有权
标题翻译：量子线栅极器件及其制造方法
公开(公告)号：US07435637B2
公开(公告)日：2008-10-14
申请号：US11105087
申请日：2005-04-12
申请人： Brian Doyle
发明人： Brian Doyle
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , B82Y10/00 , H01L21/3086 , H01L21/3088 , H01L21/823412 , H01L21/823437 , H01L29/66439 , H01L29/66795 , H01L29/775 , Y10S438/962
摘要： The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The method continues by forming a first nitride spacer mask upon the first oxide and by forming a first oxide spacer mask upon the first nitride spacer mask. Thereafter, the method continues by forming a second nitride spacer mask upon the first oxide spacer mask and by forming a plurality of channels in the substrate that are aligned to the second nitride spacer mask. A dielectric is formed upon the channel length and the method continues by forming a gate layer over the plurality of channels. Because of the inventive method and the starting scale, each of the plurality of channels is narrower than the mean free path of semiconductive electron flow therein.
摘要翻译：本发明涉及一种形成量子线栅极器件的方法。该方法包括在基底上图案化第一氧化物。优选地，第一氧化物图案被精确且均匀地间隔开以使每单位面积的量子线数量最大化。该方法通过在第一氧化物上形成第一氮化物间隔物掩模并且在第一氮化物间隔物掩模上形成第一氧化物间隔物掩模来继续。此后，该方法继续通过在第一氧化物间隔物掩模上形成第二氮化物间隔物掩模并且通过在衬底中形成与第二氮化物间隔物掩模对准的多个通道。在沟道长度上形成电介质，并且该方法继续通过在多个通道上形成栅极层。由于本发明的方法和起始标度，多个通道中的每个通道比其中的半导体电子流的平均自由程窄。

13. 发明申请

US20080085580A1 Methods for uniform doping of non-planar transistor structures 有权
标题翻译：均匀掺杂非平面晶体管结构的方法
公开(公告)号：US20080085580A1
公开(公告)日：2008-04-10
申请号：US11529963
申请日：2006-09-29
申请人： Brian Doyle , Robert Chau , Suman Datta , Jack Kavalieros
发明人： Brian Doyle , Robert Chau , Suman Datta , Jack Kavalieros
IPC分类号： H01L21/8238 , H01L29/94
CPC分类号： H01L21/823437 , H01L21/2236 , H01L21/26586 , H01L29/66803 , H01L29/7851
摘要： Methods for uniformly tip doping a silicon body of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include vertical tip ion implantation of a silicon body with at least three surfaces on a substrate followed by conformal deposition of a dielectric material. The dielectric material can be selectively etched to expose a top surface of the silicon body followed by selective re-oxidation of the top surface for form a mask. The remaining dielectric material can be removed followed by angled ion implantation of at least two sidewalls of the silicon body. The mask can be removed resulting in a silicon body with uniform doping.
摘要翻译：用于均匀尖端掺杂非平面晶体管的硅体的方法以及通过这种方法形成的器件和系统。在一个实施例中，一种方法可以包括在衬底上具有至少三个表面的硅体的垂直尖端离子注入，随后是电介质材料的共形沉积。可以选择性地蚀刻介电材料以暴露硅体的顶表面，随后选择性地再次氧化顶表面以形成掩模。可以除去剩余的电介质材料，然后对硅体的至少两个侧壁进行成角度的离子注入。可以去除掩模，从而产生均匀掺杂的硅体。

14. 发明授权

US07342277B2 Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric 有权
公开(公告)号：US07342277B2
公开(公告)日：2008-03-11
申请号：US11285763
申请日：2005-11-21
申请人： Marko Radosavljevic , Amlan Majumdar , Suman Datta , Justin Brask , Brian Doyle , Robert Chau
发明人： Marko Radosavljevic , Amlan Majumdar , Suman Datta , Justin Brask , Brian Doyle , Robert Chau
IPC分类号： H01L29/76
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/17 , H01L29/78696 , H01L51/0048 , H01L51/0541
摘要： A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.

15. 发明申请

US20070281409A1 Multi-gate carbon nano-tube transistors 有权
标题翻译：多栅极碳纳米管晶体管
公开(公告)号：US20070281409A1
公开(公告)日：2007-12-06
申请号：US11215559
申请日：2005-08-29
申请人： Yuegang Zhang , Brian Doyle , George Bourianoff
发明人： Yuegang Zhang , Brian Doyle , George Bourianoff
IPC分类号： H01L21/8234
CPC分类号： H01L29/785 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/1033 , H01L29/41791 , H01L29/42384 , H01L29/42392 , H01L29/4908 , H01L29/66795 , H01L29/772 , H01L29/7854 , H01L29/78645 , H01L29/78696 , H01L51/0048 , H01L51/0554 , Y10S977/742 , Y10S977/842 , Y10S977/938
摘要： According to one aspect of the invention, a semiconducting transistor is described. The channel portion of the transistor includes carbon nanotubes formed on top of an insulating layer which covers a local bottom gate. Source and drain conductors are located at ends of the carbon nanotubes. A gate dielectric surrounds a portion of the carbon nanotubes with a substantially uniform thickness. A local top gate is located between the source and drain conductors over the carbon nanotubes. Lower portions of the local top gate are positioned between the carbon nanotubes as the local top gate forms pi-gates or “wraparound” gates around each carbon nanotube.
摘要翻译：根据本发明的一个方面，描述了半导体晶体管。晶体管的沟道部分包括形成在覆盖局部底栅的绝缘层的顶部上的碳纳米管。源极和漏极导体位于碳纳米管的端部。栅极电介质以基本均匀的厚度围绕碳纳米管的一部分。局部顶栅位于碳纳米管之间的源极和漏极导体之间。局部顶栅的下部位于碳纳米管之间，因为局部顶栅在每个碳纳米管周围形成边界或“环绕”门。

16. 发明申请

US20070238273A1 Method of ion implanting for tri-gate devices 有权
标题翻译：三栅极器件离子注入方法
公开(公告)号：US20070238273A1
公开(公告)日：2007-10-11
申请号：US11394614
申请日：2006-03-31
申请人： Brian Doyle , Suman Datta , Jack Kavalieros , Amlan Majumdar
发明人： Brian Doyle , Suman Datta , Jack Kavalieros , Amlan Majumdar
IPC分类号： H01L21/425
CPC分类号： H01L21/26586 , H01L29/66803 , H01L29/7851
摘要： A method for ion implanting a tip source and drain region and halo region for a tri-gate field-effect transistor is described. A silicon body is implanted, in one embodiment, from six different angles to obtain ideal regions.
摘要翻译：描述了用于三栅极场效应晶体管的用于离子注入尖端源极和漏极区域和晕圈区域的方法。在一个实施例中，从六个不同的角度植入硅体，以获得理想的区域。

17. 发明申请

US20070170464A1 Transistor gate electrode having conductor material layer 有权
标题翻译：具有导体材料层的晶体管栅电极
公开(公告)号：US20070170464A1
公开(公告)日：2007-07-26
申请号：US11715703
申请日：2007-03-08
申请人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
发明人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
IPC分类号： H01L31/00
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823857 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
摘要翻译：本发明的各种实施例涉及在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有功函数的栅电极导体材料在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。

18. 发明授权

US07170120B2 Carbon nanotube energy well (CNEW) field effect transistor 有权
公开(公告)号：US07170120B2
公开(公告)日：2007-01-30
申请号：US11096984
申请日：2005-03-31
申请人： Suman Datta , Marko Radosavljevic , Brian Doyle , Jack Kavalieros , Justin Brask , Amlan Majumdar , Robert S. Chau
发明人： Suman Datta , Marko Radosavljevic , Brian Doyle , Jack Kavalieros , Justin Brask , Amlan Majumdar , Robert S. Chau
IPC分类号： H01L29/76
CPC分类号： H01L51/0508 , B82Y10/00 , H01L51/0048 , H01L51/0052 , Y10S977/762
摘要： A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped semiconductor region is between the Carbon nanotube and the delta doped region. The delta doped semiconductor region is doped opposite that of the doped semiconductor region.

19. 发明申请

US20060281236A1 Method and apparatus for improving stability of a 6T CMOS SRAM cell 有权
标题翻译：提高6T CMOS SRAM单元的稳定性的方法和装置
公开(公告)号：US20060281236A1
公开(公告)日：2006-12-14
申请号：US11508009
申请日：2006-08-21
申请人： Suman Datta , Brian Doyle , Robert Chau , Jack Kavalieros , Bo Zheng , Scott Hareland
发明人： Suman Datta , Brian Doyle , Robert Chau , Jack Kavalieros , Bo Zheng , Scott Hareland
IPC分类号： H01L21/84
CPC分类号： G11C11/412 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L27/1211 , H01L29/42384 , H01L29/66795 , H01L29/785 , H01L29/7854
摘要： The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.
摘要翻译：本发明是包括两个存取装置的CMOS SRAM单元，每个存取装置由具有单个鳍片的三栅晶体管组成; 两个上拉装置，每个上拉装置由具有单个鳍片的三栅极晶体管组成; 和两个下拉器件，每个下拉器件由具有多个鳍片的三栅晶体管组成。还提供了一种用于制造包括双鳍三栅极晶体管的CMOS SRAM单元的方法。

20. 发明申请

US20060220090A1 Semiconductor device with a high-k gate dielectric and a metal gate electrode 审中-公开
标题翻译：具有高k栅极电介质和金属栅电极的半导体器件
公开(公告)号：US20060220090A1
公开(公告)日：2006-10-05
申请号：US11089247
申请日：2005-03-23
申请人： Matthew Metz , Suman Datta , Mark Doczy , Jack Kavalieros , Justin Brask , Brian Doyle , Marko Radosavljevic , Robert Chau
发明人： Matthew Metz , Suman Datta , Mark Doczy , Jack Kavalieros , Justin Brask , Brian Doyle , Marko Radosavljevic , Robert Chau
IPC分类号： H01L29/94
CPC分类号： H01L29/516 , H01L21/28194 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/7843
摘要： A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed over a channel that is positioned within a substrate, and a metal gate electrode that is formed on the high-k gate dielectric layer. The high-k gate dielectric layer has off-state leakage characteristics that are superior to those of a silicon dioxide based gate dielectric, and on-state mobility characteristics that are superior to those of a high-k gate dielectric that comprises an isotropic material.
摘要翻译：描述半导体器件。该半导体器件包括形成在位于衬底内的沟道上的高k栅介质层和形成在高k栅介质层上的金属栅电极。高k栅极电介质层具有优于基于二氧化硅的栅极电介质的截止状态泄漏特性，以及优于包含各向同性材料的高k栅极电介质的导通状态迁移率特性。

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