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11. 发明申请

US20080181034A1 MEMORY SYSTEM WITH REDUNDANT RAM MEMORY CELLS HAVING A DIFFERENT DESIGNED CELL CIRCUIT TOPOLOGY 有权
标题翻译：具有冗余RAM记忆体的存储系统具有不同的设计细胞电路拓扑学
公开(公告)号：US20080181034A1
公开(公告)日：2008-07-31
申请号：US11627445
申请日：2007-01-26
申请人： Bradford L. Hunter , James D. Burnett , Andrew C. Russell , Shayan Zhang
发明人： Bradford L. Hunter , James D. Burnett , Andrew C. Russell , Shayan Zhang
IPC分类号： G11C7/00
CPC分类号： G11C29/846 , G11C11/41 , G11C11/412 , G11C29/816
摘要： A memory system including a random access memory (RAM) array and a corresponding redundant RAM array which stores information redundant to the RAM array, where a designed cell circuit topology of cells within the redundant RAM array differs from a designed cell circuit topology of cells within the RAM array. The redundant RAM array is selectively accessed when accessing the RAM array to store data to the redundant RAM array for failed cells of the RAM array.
摘要翻译：一种存储器系统，包括随机存取存储器（RAM）阵列和相应的冗余RAM阵列，其存储对RAM阵列冗余的信息，其中冗余RAM阵列内的单元的设计单元电路拓扑不同于设计的单元的单元电路拓扑 RAM阵列。当访问RAM阵列时，有选择地访问冗余RAM阵列，以将数据存储到RAM阵列的故障单元的冗余RAM阵列中。

12. 发明授权

US07336533B2 Electronic device and method for operating a memory circuit 有权
标题翻译：用于操作存储器电路的电子设备和方法
公开(公告)号：US07336533B2
公开(公告)日：2008-02-26
申请号：US11337775
申请日：2006-01-23
申请人： Bradford L. Hunter , James D. Burnett , Jack M. Higman
发明人： Bradford L. Hunter , James D. Burnett , Jack M. Higman
IPC分类号： G11C11/34
CPC分类号： G11C11/412 , G11C11/413
摘要： An electronic device includes a memory cell that utilizes a bi-directional low impedance, low voltage drop full pass gate to connect a bit cell to a bit write line during a write phase, and during a read phase the full pass gate can remain off and a high input impedance read port can acquire and transmit the logic state stored by the memory cell to another subsystem. The full pass gate can be implemented by connecting a P type metal semiconductor field effect transistor (PMOS) in parallel with an NMOS device and driving the gates of the transistors with a differential signal. When a write operation requires a current to flow in a first direction, the PMOS device provides a negligible voltage drop, and when the write operation requires current to flow in a second or the opposite direction, the NMOS device can provide a negligible voltage. This bi-directional low voltage drop low loss switch can increase the write margin of the memory cell wherein the high impedance read port can provide increased isolation for the stored value during the read phase increasing the performance of the memory cell.
摘要翻译：电子设备包括存储单元，其利用双向低阻抗低压降全通栅极在写入阶段期间将位单元连接到位写入线，并且在读取阶段期间，全通道栅极可以保持关断，并且高输入阻抗读取端口可以获取和传输存储器单元存储的逻辑状态到另一个子系统。可以通过与NMOS器件并联连接P型金属半导体场效应晶体管（PMOS）并用差分信号驱动晶体管的栅极来实现全通栅。当写入操作需要电流沿第一方向流动时，PMOS器件提供可忽略的电压降，并且当写操作需要电流在第二或相反方向上流动时，NMOS器件可以提供可忽略的电压。该双向低压降低损耗开关可以增加存储单元的写入裕度，其中高阻抗读取端口可以在读取阶段期间为存储的值提供增加的隔离以增加存储单元的性能。

13. 发明授权

US08456935B2 Memory and method for sensing data in a memory using complementary sensing scheme 有权
标题翻译：用于使用互补感测方案检测存储器中的数据的存储器和方法
公开(公告)号：US08456935B2
公开(公告)日：2013-06-04
申请号：US13297415
申请日：2011-11-16
申请人： Bradford L. Hunter , Shayan Zhang
发明人： Bradford L. Hunter , Shayan Zhang
IPC分类号： G11C7/12 , G11C7/06 , G11C7/08 , G11C7/22
CPC分类号： G11C7/08 , G11C7/065 , G11C11/413 , G11C2207/005
摘要： In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair (101, 104) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.
摘要翻译：在存储器（100）中，本地数据线对（116,118）被预充电到第一逻辑状态，并且全局数据线对（101,104）被预充电到第二逻辑状态。所选择的存储器单元耦合到本地数据线对（116,118）以形成差分本地数据线电压。差分局部数据线电压随后被放大以形成放大的差分局部数据线电压。全局数据线对（101,104）中选择的一个被响应于放大的差分本地数据线电压被驱动到第一逻辑状态以形成差分全局数据线电压。

14. 发明申请

US20120063249A1 MEMORY AND METHOD FOR SENSING DATA IN A MEMORY USING COMPLEMENTARY SENSING SCHEME 有权
标题翻译：使用补充感测方案在存储器中感测数据的存储器和方法
公开(公告)号：US20120063249A1
公开(公告)日：2012-03-15
申请号：US13297415
申请日：2011-11-16
申请人： Bradford L. Hunter , Shayan Zhang
发明人： Bradford L. Hunter , Shayan Zhang
IPC分类号： G11C7/12
CPC分类号： G11C7/08 , G11C7/065 , G11C11/413 , G11C2207/005
摘要： In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair (101, 104) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.
摘要翻译：在存储器（100）中，本地数据线对（116,118）被预充电到第一逻辑状态，并且全局数据线对（101,104）被预充电到第二逻辑状态。所选择的存储器单元耦合到本地数据线对（116,118）以形成差分本地数据线电压。差分局部数据线电压随后被放大以形成放大的差分局部数据线电压。全局数据线对（101,104）中选择的一个被响应于放大的差分本地数据线电压被驱动到第一逻辑状态以形成差分全局数据线电压。

15. 发明申请

US20090058473A1 ACTIVE PRE-EMPHASIS FOR PASSIVE RC NETWORKS 审中-公开
标题翻译：用于被动RC网络的主动预测
公开(公告)号：US20090058473A1
公开(公告)日：2009-03-05
申请号：US11850347
申请日：2007-09-05
申请人： Bradford L. Hunter
发明人： Bradford L. Hunter
IPC分类号： G11C27/02 , G06F17/50 , H04B1/10
CPC分类号： G06F17/5036 , G11C27/026
摘要： An approach that provides active pre-emphasis for a passive RC network is described. In one embodiment, there is a circuit that comprises an RC filter including a resistive divider formed from a first resistor and a second resistor and a filtering capacitor. The first resistor is configured to receive an input voltage and the second resistor and filtering capacitor are in parallel and configured to generate a reference voltage that is a percentage of the input voltage. An operational amplifier is coupled to the RC filter. A first multiplexer controlled by a pulse pre-emphasis signal is coupled to the operational amplifier and the RC filter. A second multiplexer controlled by a sample and hold clocking signal has inputs that are coupled to the first multiplexer and ground.
摘要翻译：描述了为被动RC网络提供主动预加重的方法。在一个实施例中，存在包括RC滤波器的电路，RC滤波器包括由第一电阻器和第二电阻器形成的电阻分压器和滤波电容器。第一电阻器被配置为接收输入电压，并且第二电阻器和滤波电容器并联并且被配置为产生作为输入电压百分比的参考电压。运算放大器耦合到RC滤波器。由脉冲预加重信号控制的第一多路复用器耦合到运算放大器和RC滤波器。由采样和保持时钟信号控制的第二多路复用器具有耦合到第一多路复用器和地的输入。

16. 发明申请

US20080091990A1 CONTROLLED RELIABILITY IN AN INTEGRATED CIRCUIT 有权
标题翻译：集成电路中控制的可靠性
公开(公告)号：US20080091990A1
公开(公告)日：2008-04-17
申请号：US11536342
申请日：2006-09-28
申请人： Klas M. Bruce , Andrew C. Russell , Shayan Zhang , Bradford L. Hunter
发明人： Klas M. Bruce , Andrew C. Russell , Shayan Zhang , Bradford L. Hunter
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G11C5/147 , G11C29/02 , G11C29/021 , G11C29/028
摘要： Methods and systems for configuring characteristics associated with at least one portion of a memory array comprising addressable units are provided. In one aspect, a method for controlling a power supply voltage for a memory array comprises detecting whether an error occurred in performing a read operation on an addressable unit of the memory array using a first power supply voltage coupled to the memory array. The method further comprises incrementing an error counter for tracking an error count associated with the memory array and switching the memory array to a second power supply voltage if the error count is equal to or exceeds an error threshold for the memory array. The method further comprises, based on at least one condition, switching the memory array to the first power supply voltage and resetting the error counter to an initial value.
摘要翻译：提供了用于配置与包括可寻址单元的存储器阵列的至少一部分相关联的特性的方法和系统。一方面，一种用于控制存储器阵列的电源电压的方法包括使用耦合到存储器阵列的第一电源电压来检测在对存储器阵列的可寻址单元执行读取操作时是否发生错误。该方法还包括增加误差计数器以跟踪与存储器阵列相关联的误差计数，并且如果误差计数等于或超过存储器阵列的误差阈值，则将存储器阵列切换到第二电源电压。该方法还包括基于至少一个条件，将存储器阵列切换到第一电源电压并将错误计数器重置为初始值。

17. 发明申请

US20080082873A1 MINIMUM MEMORY OPERATING VOLTAGE TECHNIQUE 有权
标题翻译：最小存储器工作电压技术
公开(公告)号：US20080082873A1
公开(公告)日：2008-04-03
申请号：US11468458
申请日：2006-08-30
申请人： Andrew C. Russell , David R. Bearden , Bradford L. Hunter , Shayan Zhang
发明人： Andrew C. Russell , David R. Bearden , Bradford L. Hunter , Shayan Zhang
IPC分类号： G11C29/00
CPC分类号： G11C5/147 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50016 , G11C2029/5004
摘要： A method includes an integrated circuit with a memory. The memory operates with an operating voltage. A value of a minimum operating voltage of the memory is determined. The value of the minimum operating voltage is stored in a non-volatile memory location that maybe a non-volatile register. This minimum operating voltage information can then be used in determining when an alternative power supply voltage may be switched to the memory or ensuring that the minimum voltage is otherwise met. The minimum voltage can be used only internal to the integrated circuit or also provided externally to a user.
摘要翻译：一种方法包括具有存储器的集成电路。存储器工作在工作电压。确定存储器的最小工作电压的值。最小工作电压的值存储在可能是非易失性寄存器的非易失性存储器位置。然后可以使用该最小工作电压信息来确定什么时候可以将替代电源电压切换到存储器或确保以其他方式满足最小电压。最小电压只能用于集成电路内部，也可以在用户外部使用。

18. 发明授权

US09110488B2 Wide-bandwidth linear regulator 有权
标题翻译：宽带线性稳压器
公开(公告)号：US09110488B2
公开(公告)日：2015-08-18
申请号：US13154840
申请日：2011-06-07
申请人： Bradford L. Hunter , Todd M. Rasmus
发明人： Bradford L. Hunter , Todd M. Rasmus
IPC分类号： G05F1/00 , G05F1/575 , G05F1/565 , G05F1/56
CPC分类号： G05F1/575 , G05F1/56
摘要： A linear regulator and a method of regulating a supply voltage are provided. Embodiments include a linear regulator with a first feedback loop and a second feedback loop. The first feedback loop is characterized by a first bandwidth and a first gain. The first feedback loop includes a first amplifier characterized by an output impedance which is significantly reduced in order to maximize the bandwidth of the first feedback loop when driving the capacitance of a control input of a series pass element. The second feedback loop is characterized by a second bandwidth and a second gain. The second feedback loop includes a second amplifier that controls the current in the first amplifier in the first feedback loop.
摘要翻译：提供线性调节器和调节电源电压的方法。实施例包括具有第一反馈回路和第二反馈回路的线性调节器。第一反馈回路的特征在于第一带宽和第一增益。第一反馈回路包括第一放大器，其特征在于输出阻抗显着减小，以便在驱动串联通过元件的控制输入的电容时使第一反馈环路的带宽最大化。第二反馈回路的特征在于第二带宽和第二增益。第二反馈回路包括控制第一反馈回路中的第一放大器中的电流的第二放大器。

19. 发明授权

US07684264B2 Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM array 有权
标题翻译：具有RAM阵列和冗余RAM存储单元的存储器系统具有与非冗余RAM阵列的单元不同的设计单元电路拓扑
公开(公告)号：US07684264B2
公开(公告)日：2010-03-23
申请号：US11627445
申请日：2007-01-26
申请人： Bradford L. Hunter , James D. Burnett , Andrew C. Russell , Shayan Zhang
发明人： Bradford L. Hunter , James D. Burnett , Andrew C. Russell , Shayan Zhang
IPC分类号： G11C7/00
CPC分类号： G11C29/846 , G11C11/41 , G11C11/412 , G11C29/816
摘要： A memory system including a random access memory (RAM) array and a corresponding redundant RAM array which stores information redundant to the RAM array, where a designed cell circuit topology of cells within the redundant RAM array differs from a designed cell circuit topology of cells within the RAM array. The redundant RAM array is selectively accessed when accessing the RAM array to store data to the redundant RAM array for failed cells of the RAM array.
摘要翻译：一种存储器系统，包括随机存取存储器（RAM）阵列和相应的冗余RAM阵列，其存储对RAM阵列冗余的信息，其中冗余RAM阵列内的单元的设计单元电路拓扑不同于设计的单元的单元电路拓扑 RAM阵列。当访问RAM阵列时，有选择地访问冗余RAM阵列，以将数据存储到RAM阵列的故障单元的冗余RAM阵列中。

20. 发明授权

US07523373B2 Minimum memory operating voltage technique 有权
标题翻译：最低内存工作电压技术
公开(公告)号：US07523373B2
公开(公告)日：2009-04-21
申请号：US11468458
申请日：2006-08-30
申请人： Andrew C. Russell , David R. Bearden , Bradford L. Hunter , Shayan Zhang
发明人： Andrew C. Russell , David R. Bearden , Bradford L. Hunter , Shayan Zhang
IPC分类号： G01R31/30
CPC分类号： G11C5/147 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50016 , G11C2029/5004
摘要： A method includes an integrated circuit with a memory. The memory operates with an operating voltage. A value of a minimum operating voltage of the memory is determined. The value of the minimum operating voltage is stored in a non-volatile memory location that maybe a non-volatile register. This minimum operating voltage information can then be used in determining when an alternative power supply voltage may be switched to the memory or ensuring that the minimum voltage is otherwise met. The minimum voltage can be used only internal to the integrated circuit or also provided externally to a user.
摘要翻译：一种方法包括具有存储器的集成电路。存储器工作在工作电压。确定存储器的最小工作电压值。最小工作电压的值存储在可能是非易失性寄存器的非易失性存储器位置。然后可以使用该最小工作电压信息来确定什么时候可以将替代电源电压切换到存储器或确保以其他方式满足最小电压。最小电压只能用于集成电路内部，也可以在用户外部使用。

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