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    • 11. 发明授权
    • Grainless material for calibration sample
    • 用于校准样品的粗糙材料
    • US06459482B1
    • 2002-10-01
    • US09729294
    • 2000-12-04
    • Bhanwar SinghRamkumar SubramanianKhoi A. PhanBharath RangarajanMichael K. TempletonSanjay K. YedurBryan K. Choo
    • Bhanwar SinghRamkumar SubramanianKhoi A. PhanBharath RangarajanMichael K. TempletonSanjay K. YedurBryan K. Choo
    • G01J110
    • H01J37/28H01J2237/2826
    • The present invention provides SEM systems, SEM calibration standards, and SEM calibration methods that improved accuracy in critical dimension measurements. The calibration standards have features formed with an amorphous material such as amorphous silicon. Amorphous materials lack the crystal grain structure of materials such as polysilicon and are capable of providing sharper edged features and higher accuracy patterns than grained materials. The amorphous material can be bound to a silicon wafer substrate through an intermediate layer of material, such as silicon dioxide. Where the intermediate layer is insulating material, as is silicon dioxide, the intermediate layer may be patterned with gaps to provide for electrical communication between the amorphous silicon and the silicon wafer. Charges imparted to the amorphous silicon during electron beam scanning may thereby drain to the silicon wafer rather than accumulating to a level where they would distort the electron beam.
    • 本发明提供SEM系统,SEM校准标准和SEM校准方法,提高了临界尺寸测量的精度。 校准标准品具有非晶体材料如非晶硅形成的特征。 无定形材料缺乏诸如多晶硅的材料的晶粒结构,并且能够提供比颗粒材料更尖锐的边缘特征和更高精度的图案。 非晶材料可以通过诸如二氧化硅的材料的中间层与硅晶片衬底结合。 在中间层是绝缘材料的情况下,如二氧化硅那样,中间层可以用间隙图案化以提供非晶硅和硅晶片之间的电连通。 因此,在电子束扫描期间赋予非晶硅的电荷可以从而被排出到硅晶片,而不是积聚到它们会使电子束变形的水平。
    • 12. 发明授权
    • Deliberate void in innerlayer dielectric gapfill to reduce dielectric constant
    • 内层介质间隙填料中的有意的空隙以降低介电常数
    • US06445072B1
    • 2002-09-03
    • US09617158
    • 2000-07-17
    • Ramkumar SubramanianBhanwar SinghMichael K. TempletonBharath Rangarajan
    • Ramkumar SubramanianBhanwar SinghMichael K. TempletonBharath Rangarajan
    • H01L214763
    • H01L21/7682Y10S977/897
    • One aspect of the present invention relates to a method of forming an innerlayer dielectric, involving the steps of providing a substrate having at least two metal lines thereon; providing a conformal insulation layer over the substrate and metal lines; forming a second insulation layer over the conformal insulation layer, the second insulation layer containing a void positioned between two metal lines; at least one of thinning and planarizing the second insulation layer; and forming a third insulation layer over the second insulation layer. Another aspect of the present invention relates to an innerlayer dielectric semiconductor structure, containing a semiconductor substrate having at least two metal lines thereon; a conformal insulation layer over the semiconductor substrate and metal lines, the conformal insulation layer having a substantially uniform thickness from about 250 Å to about 5,000 Å; a second insulation layer over the conformal insulation layer, the second insulation layer containing a void positioned between two metal lines; and a third insulation layer over the second insulation layer.
    • 本发明的一个方面涉及一种形成内层电介质的方法,包括以下步骤:提供其上具有至少两条金属线的基底; 在衬底和金属线上提供保形绝缘层; 在所述保形绝缘层上形成第二绝缘层,所述第二绝缘层包含位于两条金属线之间的空隙; 将所述第二绝缘层变薄和平坦化的至少一个; 以及在所述第二绝缘层上形成第三绝缘层。 本发明的另一方面涉及一种内层电介质半导体结构,其包含其上具有至少两条金属线的半导体衬底; 半导体衬底和金属线上的共形绝缘层,保形绝缘层具有从大约至大约等于的大致均匀的厚度; 在保形绝缘层之上的第二绝缘层,所述第二绝缘层包含位于两个金属线之间的空隙; 以及在所述第二绝缘层上的第三绝缘层。
    • 14. 发明授权
    • Use of silicon oxynitride ARC for metal layers
    • 氧氮化硅ARC用于金属层
    • US06326231B1
    • 2001-12-04
    • US09207562
    • 1998-12-08
    • Ramkumar SubramanianBhanwar SinghSanjay K. YedurMarina V. PlatChristopher F. LyonsBharath RangarajanMichael K. Templeton
    • Ramkumar SubramanianBhanwar SinghSanjay K. YedurMarina V. PlatChristopher F. LyonsBharath RangarajanMichael K. Templeton
    • H01L2100
    • H01L21/32139H01L21/0276H01L21/3143H01L21/3145
    • In one embodiment, the present invention relates to a method of forming a silicon oxynitride antireflection coating over a metal layer, involving the steps of providing a semiconductor substrate comprising the metal layer over at least part of the semiconductor substrate; depositing a silicon oxynitride layer over the metal layer having a thickness from about 100 Å to about 150 Å; and forming an oxide layer having a thickness from about 5 Å to about 50 Å over the silicon oxynitride layer to provide the silicon oxynitride antireflection coating. In another embodiment, the present invention relates to a method of reducing an apparent reflectivity of a metal layer having a first reflectivity in a semiconductor structure, involing forming a silicon oxynitride antireflection coating over the metal layer; wherein the silicon oxynitride antireflection coating formed over the metal layer has a second reflectivity and is formed by depositing silicon oxynitride on the metal layer by chemical vapor deposition and forming an oxide layer over the oxynitride, and the difference between the first reflectivity and the second reflectivity is at least about 60%.
    • 在一个实施方案中,本发明涉及在金属层上形成氮氧化硅抗反射涂层的方法,包括以下步骤:在半导体衬底的至少一部分上提供包括金属层的半导体衬底; 在所述金属层上沉积厚度为约至约的氧氮化硅层; 并在氮氧化硅层上形成厚度约为5-20埃的氧化物层,以提供氮氧化硅抗反射涂层。 在另一个实施方案中,本发明涉及一种在半导体结构中减少具有第一反射率的金属层的表观反射率的方法,包括在金属层上形成氮氧化硅抗反射涂层; 其中形成在所述金属层上的所述氧氮化硅抗反射涂层具有第二反射率,并且通过化学气相沉积在所述金属层上沉积氧氮化硅并在所述氧氮化物上形成氧化物层,并且所述第一反射率和所述第二反射率之间的差异 至少约60%。
    • 15. 发明授权
    • System and method for active control of BPSG deposition
    • 用于主动控制BPSG沉积的系统和方法
    • US06828162B1
    • 2004-12-07
    • US09894434
    • 2001-06-28
    • Arvind HalliyalBhanwar SinghMichael K. TempletonRamkumar Subramanian
    • Arvind HalliyalBhanwar SinghMichael K. TempletonRamkumar Subramanian
    • H01L2100
    • H01L21/67253G01N21/4738H01L21/02129H01L21/31625
    • A system for monitoring and controlling a boron phosphorous doped silicon oxide (BPSG) deposition and reflow process is provided. The system includes one or more light sources, each light source directing light to one or more portions of a wafer upon which BPSG is deposited. Light reflected from the BPSG is collected by a measuring system, which processes the collected light. Light passing through the BPSG may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the conformality of the BPSG deposition of the respective portions of the wafer. The measuring system provides BPSG deposition related data to a processor that determines the BPSG deposition of the respective portions of the wafer. The system also includes a plurality of reflow controlling devices, each such device corresponding to a respective portion of the wafer and providing for the heating and/or cooling thereof. The processor selectively controls the reflow controlling devices so as to regulate temperature of the respective portions of the wafer.
    • 提供了一种用于监测和控制硼磷掺杂氧化硅(BPSG)沉积和回流工艺的系统。 该系统包括一个或多个光源,每个光源将光引导到沉积BPSG的晶片的一个或多个部分。 从BPSG反射的光被测量系统收集,该系统处理收集的光。 通过BPSG的光可以类似地由处理所收集的光的测量系统收集。 所收集的光表示晶片的各个部分的BPSG沉积的一致性。 测量系统将BPSG沉积相关数据提供给确定晶片各部分的BPSG沉积的处理器。 该系统还包括多个回流控制装置,每个这样的装置对应于晶片的相应部分并提供加热和/或冷却。 处理器选择性地控制回流控制装置,以便调节晶片各部分的温度。
    • 17. 发明授权
    • Active control of phase shift mask etching process
    • 主动控制相移掩模蚀刻工艺
    • US06562248B1
    • 2003-05-13
    • US09817518
    • 2001-03-26
    • Ramkumar SubramanianBhanwar SinghMichael K. Templeton
    • Ramkumar SubramanianBhanwar SinghMichael K. Templeton
    • G01N2100
    • G03F1/84G03F1/26
    • A system for monitoring and controlling aperture etching in a complimentary phase shift mask is provided. The system includes one or more light sources, each light source directing light to one or more apertures etched on a mask. Light reflected from the apertures is collected by a measuring system, which processes the collected light. Light passing through the apertures may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the depth and/or width of the openings on the mask. The measuring system provides depth and/or width related data to a processor that determines the acceptability of the aperture depth and/or width. The system also includes a plurality of etching devices associated with etching apertures in the mask. The processor selectively controls the etching devices so as to regulate aperture etching.
    • 提供了一种用于在补偿相移掩模中监测和控制孔蚀刻的系统。 该系统包括一个或多个光源,每个光源将光引导到在掩模上蚀刻的一个或多个孔。 从孔径反射的光由测量系统收集,该系统处理所收集的光。 通过孔的光可以类似地由处理收集的光的测量系统收集。 收集的光指示掩模上的开口的深度和/或宽度。 测量系统向确定孔径深度和/或宽度的可接受性的处理器提供深度和/或宽度相关数据。 该系统还包括与掩模中的孔蚀刻相关联的多个蚀刻装置。 处理器选择性地控制蚀刻装置以调节孔径蚀刻。
    • 19. 发明授权
    • Nozzle arm movement for resist development
    • 喷嘴臂运动用于抗蚀剂开发
    • US06541184B1
    • 2003-04-01
    • US09655979
    • 2000-09-06
    • Ramkumar SubramanianKhoi A. PhanBharath RangarajanBhanwar SinghMichael K. TempletonSanjay K. Yedur
    • Ramkumar SubramanianKhoi A. PhanBharath RangarajanBhanwar SinghMichael K. TempletonSanjay K. Yedur
    • G03C556
    • H01L21/6715G03F7/3028
    • A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a multiple tip nozzle and a movement system that moves the nozzle to an operating position above a central region of a photoresist material layer located on a substrate, and applies a volume of developer as the nozzle scan moves across a predetermined path. The movement system moves the nozzle in two dimensions by providing an arm that has a first arm member that is pivotable about a first rotational axis and a second arm member that is pivotable about a second rotational axis or is movable along a translational axis. The system also provides a measurement system that measures the thickness uniformity of the developed photoresist material layer disposed on a test wafer. The thickness uniformity data is used to reconfigure the predetermined path of the nozzle as the developer is applied. The thickness uniformity data can also be used to adjust the volume of developer applied along the path and/or the volume flow rate.
    • 提供了一种有助于在光致抗蚀剂材料层上施加均匀的显影剂材料层的系统和方法。 该系统包括多个尖端喷嘴和运动系统,该运动系统将喷嘴移动到位于基板上的光致抗蚀剂材料层的中心区域上方的操作位置,并且当喷嘴扫描移动穿过预定路径时施加一定体积的显影剂。 移动系统通过提供具有第一臂构件的臂来移动喷嘴,该臂具有可围绕第一旋转轴线枢转的第一臂构件和可围绕第二旋转轴线枢转或可沿着平移轴线移动的第二臂构件。 该系统还提供了测量设置在测试晶片上的显影的光致抗蚀剂材料层的厚度均匀性的测量系统。 当施加显影剂时,厚度均匀性数据用于重新配置喷嘴的预定路径。 厚度均匀性数据也可用于调节沿路径施加的显影剂的体积和/或体积流量。
    • 20. 发明授权
    • Integrated equipment to drain water-hexane developer for pattern collapse
    • 集成设备排出水 - 己烷显影剂,用于图案塌陷
    • US06513996B1
    • 2003-02-04
    • US10050436
    • 2002-01-16
    • Ramkumar SubramanianMichael K. TempletonBhanwar Singh
    • Ramkumar SubramanianMichael K. TempletonBhanwar Singh
    • G03B500
    • G03F7/3021
    • One aspect of the present invention relates to a method and an apparatus for rinsing a substrate during a development process to mitigate pattern collapse. The apparatus includes a bath chamber; a substrate holder disposed in the bath chamber for holding the substrate having a resist pattern formed thereon; a first nozzle for dispensing a first rinsing solution having a first density and first surface tension into the bath chamber; a second nozzle for dispensing a second rinsing solution having a second density and second surface tension, which is less than the first rinsing solution, into the bath chamber; a drain disposed in a bottom portion of the bath chamber; and a controlling system operatively coupled to the first nozzle, the second nozzle and the drain designed to regulate and coordinate the operation of the first nozzle, the second nozzle and the drain.
    • 本发明的一个方面涉及一种用于在显影过程中漂洗衬底以减轻图案崩溃的方法和装置。 该装置包括浴室; 设置在所述浴室中用于保持形成有抗蚀剂图案的所述基板的基板保持架; 用于将具有第一密度和第一表面张力的第一冲洗溶液分配到所述浴室中的第一喷嘴; 第二喷嘴,用于将具有小于第一冲洗溶液的第二密度和第二表面张力的第二冲洗溶液分配到浴室中; 排水口,其设置在所述浴室的底部; 以及可操作地联接到第一喷嘴,第二喷嘴和排水口的设计用于调节和协调第一喷嘴,第二喷嘴和排水管的操作的控制系统。