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11. 发明授权

US08829572B2 Structure and layout of a FET prime cell 有权
标题翻译： FET素电池的结构和布局
公开(公告)号：US08829572B2
公开(公告)日：2014-09-09
申请号：US13398408
申请日：2012-02-16
申请人： Basanth Jagannathan , John J. Pekarik , Christopher M. Schnabel
发明人： Basanth Jagannathan , John J. Pekarik , Christopher M. Schnabel
IPC分类号： H01L29/66 , H01L27/088 , H01L21/70 , H01L23/552
CPC分类号： H01L29/78 , H01L23/4824 , H01L29/1087
摘要： Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.
摘要翻译：制造半导体器件的方法包括在衬底中形成源极和漏极，在源极和漏极之间的衬底上形成栅极，形成与源电接触的衬底接触，以及形成与源极的电接触，漏极和栅极以及基板。

12. 发明授权

US07741857B2 System and method for de-embedding a device under test employing a parametrized netlist 失效
标题翻译：使用参数化网表解嵌入被测设备的系统和方法
公开(公告)号：US07741857B2
公开(公告)日：2010-06-22
申请号：US12043169
申请日：2008-03-06
申请人： Basanth Jagannathan , Zhenrong Jin , Hongmei Li
发明人： Basanth Jagannathan , Zhenrong Jin , Hongmei Li
IPC分类号： G01R35/00 , G01D18/00 , G01P21/00
CPC分类号： G01R27/32 , G01R35/00
摘要： S-parameter data is measured on an embedded device test structure, an open dummy, and a short dummy. A 4-port network of the pad set parasitics of the embedded device test structure is modeled by a parameterized netlist containing a lumped element network having at least one parameterized lumped element. The S-parameter data across a range of measurement frequencies is fitted with the parameterized netlist employing the at least one parameterized lumped element as at least one fitting parameter for the S-parameter data. Thus, the fitting method is a multi-frequency fitting for the at least one parameterized lumped element. A 4-port Y-parameter (admittance parameter) is obtained from the fitted parameterized netlist. The Y-parameter of the device under test is obtained from the measured admittance of the embedded device test structure and the calculated 4-port Y parameter.
摘要翻译： S参数数据是在嵌入式设备测试结构上测量的，一个开放虚拟的和一个短虚拟的。嵌入式设备测试结构的焊盘组寄生效应的4端口网络由包含具有至少一个参数化集总元件的集总元件网络的参数化网表建模。跨越测量频率范围的S参数数据与采用至少一个参数化集总元件的参数化网表相配合，作为S参数数据的至少一个拟合参数。因此，拟合方法是用于至少一个参数化的集总元件的多频率拟合。从拟合的参数化网表获得4端口Y参数（导纳参数）。被测器件的Y参数是从嵌入式器件测试结构的测量导纳和计算的4端口Y参数获得的。

13. 发明授权

US07183576B2 Epitaxial and polycrystalline growth of Si1-x-yGexCy and Si1-yCy alloy layers on Si by UHV-CVD 有权
标题翻译： Si1-x-yGexCy和Si1-yCy合金层通过UHV-CVD在Si上的外延和多晶生长
公开(公告)号：US07183576B2
公开(公告)日：2007-02-27
申请号：US10775514
申请日：2004-02-10
申请人： Jack Oon Chu , Basanth Jagannathan , Alfred Grill , Bernard Steele Meyerson , John Albrecht Ott
发明人： Jack Oon Chu , Basanth Jagannathan , Alfred Grill , Bernard Steele Meyerson , John Albrecht Ott
IPC分类号： H01L29/16 , H01L29/737
CPC分类号： C23C16/325 , C23C16/32 , C30B25/02 , C30B29/52 , H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02505 , H01L21/02529 , H01L21/02532 , H01L21/02694 , Y10T428/12674
摘要： A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitakial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon
摘要翻译：描述了一种用于在热壁，等温UHV-CVD系统中在多个基板上沉积单晶，硅碳和硅锗碳外延膜的方法和装置。特别地，描述了在350℃至750℃的范围内的多晶片低温生长技术，用于在Si和SiGe膜中外延引入碳，其具有非常突然且明确限定的结，但没有任何相关的氧背景污染。优选地，这些成膜SiC和SiGeC膜是原位掺杂的p型或n型，并且存在低浓度的碳<20 20 -3 -3，生长的p型或n型掺杂物分布可以承受炉退火至850℃的温度和快速热退火温度至1000℃

14. 发明授权

US07173274B2 Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology 有权
标题翻译：在硅/硅锗外延层中引入碳以提高Si-Ge双极技术的产量
公开(公告)号：US07173274B2
公开(公告)日：2007-02-06
申请号：US10953378
申请日：2004-09-29
申请人： Jack Oon Chu , Douglas Duane Coolbaugh , James Stuart Dunn , David R. Greenberg , David L. Harame , Basanth Jagannathan , Robb Allen Johnson , Louis D. Lanzerotti , Kathryn Turner Schonenberg , Ryan Wayne Wuthrich
发明人： Jack Oon Chu , Douglas Duane Coolbaugh , James Stuart Dunn , David R. Greenberg , David L. Harame , Basanth Jagannathan , Robb Allen Johnson , Louis D. Lanzerotti , Kathryn Turner Schonenberg , Ryan Wayne Wuthrich
IPC分类号： H01L29/06 , H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0339
CPC分类号： H01L29/66242 , H01L21/02381 , H01L21/02447 , H01L21/02529 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L29/1004 , H01L29/161 , H01L29/7378
摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.
摘要翻译：提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。

15. 发明授权

US06780695B1 BiCMOS integration scheme with raised extrinsic base 有权
标题翻译： BiCMOS整合方案具有突出的外在基础
公开(公告)号：US06780695B1
公开(公告)日：2004-08-24
申请号：US10249563
申请日：2003-04-18
申请人： Huajie Chen , Seshadri Subbanna , Basanth Jagannathan , Gregory G. Freeman , David C. Ahlgren , David Angell , Kathryn T. Schonenberg , Kenneth J. Stein , Fen F. Jamin
发明人： Huajie Chen , Seshadri Subbanna , Basanth Jagannathan , Gregory G. Freeman , David C. Ahlgren , David Angell , Kathryn T. Schonenberg , Kenneth J. Stein , Fen F. Jamin
IPC分类号： H01L218238
CPC分类号： H01L21/8249 , H01L27/0623
摘要： A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area. At least one bipolar transistor having a raised extrinsic base is then formed in the at least one opening.
摘要翻译：提供一种形成具有凸起的外在基极的BiCMOS集成电路的方法。该方法包括首先在位于具有用于形成至少一个双极晶体管的器件区域的衬底的顶部的栅极电介质的表面上方形成多晶硅层，以及用于形成至少一个互补金属氧化物半导体（CMOS）晶体管的器件区域）。然后将多晶硅层图案化以在器件区域上提供用于形成至少一个双极晶体管及其周围区域的牺牲多晶硅层，同时在用于形成至少一个CMOS晶体管的器件区域中提供至少一个栅极导体。然后围绕至少一个栅极导体的每一个形成至少一对间隔物，然后选择性地去除双极器件区域上的牺牲多晶硅层的一部分以在双极器件区域中提供至少一个开口。然后在至少一个开口中形成至少一个具有凸起的非本征基极的双极晶体管。

16. 发明授权

US06750119B2 Epitaxial and polycrystalline growth of Si1-x-yGexCy and Si1-yCy alloy layers on Si by UHV-CVD 有权
公开(公告)号：US06750119B2
公开(公告)日：2004-06-15
申请号：US09838892
申请日：2001-04-20
申请人： Jack Oon Chu , Basanth Jagannathan , Alfred Grill , Bernard Steele Meyerson , John Albrecht Ott
发明人： Jack Oon Chu , Basanth Jagannathan , Alfred Grill , Bernard Steele Meyerson , John Albrecht Ott
IPC分类号： H01L2120
CPC分类号： C23C16/325 , C23C16/32 , C30B25/02 , C30B29/52 , H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02505 , H01L21/02529 , H01L21/02532 , H01L21/02694 , Y10T428/12674
摘要： A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon

17. 发明授权

US08187930B2 Structure and layout of a FET prime cell 有权
标题翻译： FET素电池的结构和布局
公开(公告)号：US08187930B2
公开(公告)日：2012-05-29
申请号：US11923686
申请日：2007-10-25
申请人： Basanth Jagannathan , John J. Pekarik , Christopher M. Schnabel
发明人： Basanth Jagannathan , John J. Pekarik , Christopher M. Schnabel
IPC分类号： H01L21/337
CPC分类号： H01L29/78 , H01L23/4824 , H01L29/1087
摘要： Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.
摘要翻译：制造半导体器件的方法包括在衬底中形成源极和漏极，在源极和漏极之间的衬底上形成栅极，形成与源电接触的衬底接触，以及形成与源极的电接触，漏极和栅极以及基板。

18. 发明授权

US07713829B2 Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology 失效
标题翻译：在硅/硅锗外延层中引入碳以提高Si-Ge双极技术的产量
公开(公告)号：US07713829B2
公开(公告)日：2010-05-11
申请号：US11562735
申请日：2006-11-22
申请人： Jack Oon Chu , Douglas Duane Coolbaugh , James Stuart Dunn , David R. Greenberg , David L. Harame , Basanth Jagannathan , Robb Allen Johnson , Louis D. Lanzerotti , Kathryn Turner Schonenberg , Ryan Wayne Wuthrich
发明人： Jack Oon Chu , Douglas Duane Coolbaugh , James Stuart Dunn , David R. Greenberg , David L. Harame , Basanth Jagannathan , Robb Allen Johnson , Louis D. Lanzerotti , Kathryn Turner Schonenberg , Ryan Wayne Wuthrich
IPC分类号： H01L21/8222 , H01L29/737
CPC分类号： H01L29/66242 , H01L21/02381 , H01L21/02447 , H01L21/02529 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L29/1004 , H01L29/161 , H01L29/7378
摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.
摘要翻译：提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。

19. 发明授权

US06787427B2 Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics 有权
标题翻译：制造具有受控电流增益和改进的击穿电压特性的SiGe HBT的方法
公开(公告)号：US06787427B2
公开(公告)日：2004-09-07
申请号：US10676171
申请日：2003-10-01
申请人： David R. Greenberg , Basanth Jagannathan , Shwu-Jen Jeng , Joseph T. Kocis , Samuel C. Ramac , David M. Rockwell
发明人： David R. Greenberg , Basanth Jagannathan , Shwu-Jen Jeng , Joseph T. Kocis , Samuel C. Ramac , David M. Rockwell
IPC分类号： H01L21331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.
摘要翻译：提供一种制造SiGe异质结双极晶体管（HBT）的方法，其导致具有可控电流增益和改善的击穿电压的SiGe HBT。具有这些特性的SiGe HBT通过在图案化的SiGe基底结构顶上形成原位P掺杂的发射极层来制造。原位P掺杂发射极层是原位P掺杂的a：Si和原位P掺杂多晶硅的双层。包括上述双层发射体的SiGe HBT结构也在此描述。

20. 发明授权

US06656809B2 Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics 失效
标题翻译：制造具有受控电流增益和改进的击穿电压特性的SiGe HBT的方法
公开(公告)号：US06656809B2
公开(公告)日：2003-12-02
申请号：US10047975
申请日：2002-01-15
申请人： David R. Greenberg , Basanth Jagannathan , Shwu-Jen Jeng , Joseph T. Kocis , Samuel C. Ramac , David M. Rockwell
发明人： David R. Greenberg , Basanth Jagannathan , Shwu-Jen Jeng , Joseph T. Kocis , Samuel C. Ramac , David M. Rockwell
IPC分类号： G01R3126
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.
摘要翻译：提供一种制造SiGe异质结双极晶体管（HBT）的方法，其导致具有可控电流增益和改善的击穿电压的SiGe HBT。具有这些特性的SiGe HBT通过在图案化的SiGe基底结构顶上形成原位P掺杂的发射极层来制造。原位P掺杂发射极层是原位P掺杂的a：Si和原位P掺杂多晶硅的双层。包括上述双层发射体的SiGe HBT结构也在此描述。

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