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11. 发明授权

US5336629A Folder Bitline DRAM having access transistors stacked above trench storage capacitors, each such transistor employing a planar semiconductor body which spans adjacent capacitors 失效
标题翻译：具有堆叠在沟槽存储电容器之上的存取晶体管的文件夹位线DRAM，每个这样的晶体管采用跨越相邻电容器的平面半导体本体
公开(公告)号：US5336629A
公开(公告)日：1994-08-09
申请号：US975655
申请日：1992-11-13
申请人： Sang H. Dhong , Wei Hwang , Lewis M. Terman , Matthew R. Wordeman
发明人： Sang H. Dhong , Wei Hwang , Lewis M. Terman , Matthew R. Wordeman
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10832
摘要： A folded bitline DRAM cell is described which includes a trench capacitor and a planar-configured access transistor. The access transistor is stacked over the capacitor and has a first terminal connected thereto. The access transistor includes a planar-oriented gate. A first wordline has a minor surface in contact with the gate and a major surface that is oriented orthogonally to the gate. An insulating pedestal is positioned adjacent the gate and a passing wordline is positioned on the pedestal, the passing wordline having a major surface parallel to the first wordline. In another embodiment, the folded bitline DRAM cell includes a vertically oriented access transistor having one terminal formed on the upper extent of a contact to the trench capacitor, to provide optimum electrical connection thereto.
摘要翻译：描述了折叠的位线DRAM单元，其包括沟槽电容器和平面配置的存取晶体管。存取晶体管堆叠在电容器上，并具有与其连接的第一端子。存取晶体管包括平面取向栅极。第一字线具有与栅极接触的次表面和与栅极正交定向的主表面。绝缘基座位于门附近，并且通过的字线位于基座上，通过的字线具有与第一字线平行的主表面。在另一个实施例中，折叠的位线DRAM单元包括垂直定向的存取晶体管，其具有形成在与沟槽电容器的接触的上部范围上的一个端子，以提供与其的最佳电连接。

12. 发明授权

US5280452A Power saving semsing circuits for dynamic random access memory 失效
标题翻译：动态随机存取存储器的省电语音电路
公开(公告)号：US5280452A
公开(公告)日：1994-01-18
申请号：US729120
申请日：1991-07-12
申请人： Sang H. Dhong , Lewis M. Terman
发明人： Sang H. Dhong , Lewis M. Terman
IPC分类号： G11C11/409 , G11C11/4091 , G11C7/00 , G11C11/40
CPC分类号： G11C11/4091
摘要： A sensing circuit for a dynamic random access memory structure is disclosed having first and second bit lines, one of the bit lines being a reference bit line which is held at a precharge voltage when a sense amplifier in the sensing circuit is latched, the sense amplifier includes first and second nodes and first, second, third and fourth transistor devices, the first and second transistor devices form an N-device cross-coupled pair and the third and fourth transistor devices form a P-device cross-coupled pair. The first node is connected to the first bit line and to the second and fourth transistor devices, and the second node is connected to the first and third transistor devices. A first isolation transistor device is connected to the first bit line and a second isolation transistor device is connected to the second bit line. A first clock signal line is connected to the first isolation transistor device and a second clock signal line is connected to the second isolation transistor device. A first equalization transistor device is connected to the first bit line and a second equalization transistor device is connected to the second bit line, a voltage signal line having a voltage value V.sub.EQ thereon is connected to the first and second equalization transistor devices, and a third clock signal line is connected to the first equalization device. A fourth clock signal line is connected to the second equalization transistor device, a fifth clock signal line is connected to the first and second N devices, a sixth clock signal line is connected to the third and fourth P devices. The first, second, third, fourth and fifth and sixth clock signal lines have clock signals thereon which occur during a time sequence for precharging the first and second nodes to a precharge voltage value V.sub.EQ.
摘要翻译：公开了一种用于动态随机存取存储器结构的感测电路，其具有第一和第二位线，位线之一是当感测电路中的读出放大器被锁存时保持在预充电电压的参考位线，读出放大器包括第一和第二节点以及第一，第二，第三和第四晶体管器件，第一和第二晶体管器件形成N器件交叉耦合对，并且第三和第四晶体管器件形成P器件交叉耦合对。第一节点连接到第一位线和第二和第四晶体管器件，第二节点连接到第一和第三晶体管器件。第一隔离晶体管器件连接到第一位线，第二隔离晶体管器件连接到第二位线。第一时钟信号线连接到第一隔离晶体管器件，第二时钟信号线连接到第二隔离晶体管器件。第一均衡晶体管器件连接到第一位线，第二均衡晶体管器件连接到第二位线，其上具有电压值VEQ的电压信号线连接到第一和第二均衡晶体管器件，第三均衡晶体管器件时钟信号线连接到第一均衡装置。第四时钟信号线连接到第二均衡晶体管器件，第五时钟信号线连接到第一和第二N器件，第六时钟信号线连接到第三和第四P器件。第一，第二，第三，第四和第五和第六时钟信号线在其上具有时钟信号，其在用于将第一和第二节点预充电到预充电电压值VEQ的时间序列期间发生。

13. 发明授权

US4688063A Dynamic ram cell with MOS trench capacitor in CMOS 失效
标题翻译：具有MOS沟槽电容器的动态RAM单元
公开(公告)号：US4688063A
公开(公告)日：1987-08-18
申请号：US920916
申请日：1986-10-21
申请人： Nicky C. Lu , Tak H. Ning , Lewis M. Terman
发明人： Nicky C. Lu , Tak H. Ning , Lewis M. Terman
IPC分类号： H01L27/108 , H01L29/94 , H01L29/78
CPC分类号： H01L27/10832 , H01L29/945
摘要： This invention relates generally to Dynamic Random Access Memory (DRAM) cells and more particularly relates to a DRAM cell wherein the storage capacitor of the cell is disposed in a trench formed in a semiconductor substrate. Still more particularly, it relates to a DRAM cell wherein at least a portion of the substrate is heavily doped and forms the counterelectrode of the storage capacitor while a heavily doped polycrystalline plug disposed in the trench capacitor forms the other electrode of the storage capacitor. The DRAM cell includes a field effect access transistor disposed in a well which is opposite in conductivity type to that of the substrate. The well itself is formed in a lightly doped portion of the substrate and may be n or p-type conductivity with the other portions of the cell having conductivity types appropriate for devices fabricated in the CMOS environment. The trench capacitor extends from the surface of the well through the well and lightly doped substrate portion into the heavily doped portion of the substrate. The electrode disposed in the trench is directly connected to the source/drain of the access transistor.
摘要翻译：本发明一般涉及动态随机存取存储器（DRAM）单元，更具体地说，涉及一种DRAM单元，其中单元的存储电容器设置在形成于半导体衬底中的沟槽中。更具体地说，本发明涉及一种DRAM单元，其中基板的至少一部分被重掺杂并形成存储电容器的反电极，而设置在沟槽电容器中的重掺杂多晶硅形成存储电容器的另一个电极。 DRAM单元包括放置在与衬底的导电类型相反的阱中的场效应存取晶体管。阱本身形成在衬底的轻掺杂部分中，并且可以是n型或p型导电性，其中电池的其它部分具有适合于在CMOS环境中制造的器件的导电类型。沟槽电容器从阱的表面延伸穿过阱和轻掺杂衬底部分到衬底的重掺杂部分。设置在沟槽中的电极直接连接到存取晶体管的源极/漏极。

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