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11. 发明申请

US20130265734A1 INTERCHIP COMMUNICATION USING EMBEDDED DIELECTRIC AND METAL WAVEGUIDES 审中-公开
标题翻译：使用嵌入式电介质和金属波导的交互通信
公开(公告)号：US20130265734A1
公开(公告)日：2013-10-10
申请号：US13439646
申请日：2012-04-04
申请人： Juan A. Herbsommer , Robert F. Payne , Marco Corsi , Baher S. Haroun , Hassan Ali
发明人： Juan A. Herbsommer , Robert F. Payne , Marco Corsi , Baher S. Haroun , Hassan Ali
IPC分类号： H05K1/14 , H05K1/11
CPC分类号： G02B6/12004 , G02B6/1228 , G02B6/43 , H01L2223/6627 , H01L2224/16227 , H01L2924/15311 , H01P3/121 , H01P3/122 , H01P5/107 , H05K1/0239 , H05K1/0243 , H05K1/025 , H05K1/0274 , H05K2201/0187 , H05K2201/037 , H05K2201/09618 , H05K2201/10098
摘要： An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.
摘要翻译：提供了一种装置。存在具有封装基板和集成电路（IC）的电路组件。封装衬底具有微带线，并且IC被固定到封装衬底并且电耦合到微带线。电路板也固定到封装衬底。介质波导固定在电路板上。电介质波导具有延伸到位于电介质波导和微带线之间的过渡区域的介质芯，并且微带线被配置为与介质波导形成通信链路。

12. 发明申请

US20120086589A1 PIPELINED CONTINUOUS-TIME SIGMA DELTA MODULATOR 有权
公开(公告)号：US20120086589A1
公开(公告)日：2012-04-12
申请号：US12899205
申请日：2010-10-06
申请人： Baher S. Haroun , Venkatesh Srinivasan , Patrick Satarzadeh , Marco Corsi
发明人： Baher S. Haroun , Venkatesh Srinivasan , Patrick Satarzadeh , Marco Corsi
IPC分类号： H03M1/06 , H03M3/00
CPC分类号： H03M3/344 , H03M3/458
摘要： Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

13. 发明申请

US20130265733A1 INTERCHIP COMMUNICATION USING AN EMBEDDED DIELECTRIC WAVEGUIDE 审中-公开
标题翻译：使用嵌入式电介质波导的交互通信
公开(公告)号：US20130265733A1
公开(公告)日：2013-10-10
申请号：US13439621
申请日：2012-04-04
申请人： Juan A. Herbsommer , Robert F. Payne , Marco Corsi , Baher S. Haroun , Hassan Ali
发明人： Juan A. Herbsommer , Robert F. Payne , Marco Corsi , Baher S. Haroun , Hassan Ali
IPC分类号： H05K1/11 , H05K1/18
CPC分类号： G02B6/12004 , G02B6/1228 , G02B6/43 , H01L2223/6627 , H01L2224/16227 , H01L2924/15311 , H01P3/16 , H01P5/107 , H05K1/0239 , H05K1/0243 , H05K1/025 , H05K1/0274 , H05K2201/0187 , H05K2201/037 , H05K2201/09618 , H05K2201/10098
摘要： An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.
摘要翻译：提供了一种装置。存在具有封装基板和集成电路（IC）的电路组件。封装衬底具有微带线，并且IC被固定到封装衬底并且电耦合到微带线。电路板也固定到封装衬底。介质波导固定在电路板上。电介质波导具有延伸到位于电介质波导和微带线之间的过渡区域的介质芯，并且微带线被配置为与介质波导形成通信链路。

14. 发明申请

US20120313895A1 TOUCH SCREEN 审中-公开
标题翻译：触摸屏
公开(公告)号：US20120313895A1
公开(公告)日：2012-12-13
申请号：US13158010
申请日：2011-06-10
申请人： Baher S. Haroun , Marco Corsi , Brian P. Ginsburg , Vijay B. Rentala , Srinath M. Ramaswamy , Eunyoung Seok
发明人： Baher S. Haroun , Marco Corsi , Brian P. Ginsburg , Vijay B. Rentala , Srinath M. Ramaswamy , Eunyoung Seok
IPC分类号： G06F3/042
摘要： A method for determining the location of an object on a touch panel is provided. Initially, a pulse of terahertz radiation is transmitted through a touch panel, which formed of a dielectric material such that the pulse generates a evanescent field in a region adjacent to a touch surface of the touch panel. A reflected pulse is generated by an object located within the region adjacent to the touch surface of the touch panel, and a position of the object on the touch surface of the touch panel is triangulated at least in part from the reflected pulse.
摘要翻译：提供了一种用于确定物体在触摸面板上的位置的方法。最初，通过由介电材料形成的触摸面板传输太赫兹辐射的脉冲，使得脉冲在与触摸面板的触摸面相邻的区域中产生消逝场。反射脉冲由位于与触摸面板的触摸面相邻的区域内的物体产生，并且物体在触摸面板的触摸面上的位置至少部分地从反射脉冲进行三角测量。

15. 发明授权

US08284085B2 Pipelined continuous-time sigma delta modulator 有权
标题翻译：流水线连续时间Σ-Δ调制器
公开(公告)号：US08284085B2
公开(公告)日：2012-10-09
申请号：US12899205
申请日：2010-10-06
申请人： Baher S. Haroun , Venkatesh Srinivasan , Patrick Satarzadeh , Marco Corsi
发明人： Baher S. Haroun , Venkatesh Srinivasan , Patrick Satarzadeh , Marco Corsi
IPC分类号： H03M3/00
CPC分类号： H03M3/344 , H03M3/458
摘要： Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
摘要翻译：传统上，流水线连续时间（CT）Σ-Δ调制器（SDM）已经难以构建，至少部分是由于校准管道的困难。然而，这里提供了一种流水线CT SDM，其具有有助于被校准的架构。也就是说，该系统包括数字滤波器和其他可调整的特征，以解决输入不平衡误差以及量化泄漏噪声。

16. 发明申请

US20120261579A1 ANALOG BASEBAND CIRCUIT FOR A TERAHERTZ PHASED ARRAY SYSTEM 有权
标题翻译：用于TERAHERTZ相位阵列的模拟基带电路
公开(公告)号：US20120261579A1
公开(公告)日：2012-10-18
申请号：US13085264
申请日：2011-04-12
申请人： Srinath M. Ramaswamy , Vijay B. Rentala , Brian P. Ginsburg , Baher S. Haroun , Eunyoung Seok
发明人： Srinath M. Ramaswamy , Vijay B. Rentala , Brian P. Ginsburg , Baher S. Haroun , Eunyoung Seok
IPC分类号： G01J5/26 , G01J5/02
CPC分类号： H01Q3/26 , G01S7/288 , G01S13/426
摘要： A method for determining the position of a target is provided. Several emitted pulses of terahertz radiations are emitted from a phased array (which has several transceivers) in consecutive cycles (typically). These emitted pulses are generally configured to be reflected by a target so as to be received by the phased array within a scan range (which includes a digitization window with several sampling periods). Output signals from each of the transceivers are then combined to generate a combined signal for each cycle. The combined signal in each sampling period within the digitization window for emitted pulses is averaged to generate an averaged signal for each sampling period within the digitization window. These averaged signals are then digitized.
摘要翻译：提供了一种用于确定目标位置的方法。几个发射的太赫兹辐射脉冲从相控阵列（其具有几个收发器）以连续的周期（通常）发射。这些发射脉冲通常被配置为被目标物反射，以便在扫描范围内包括相控阵列（其包括具有多个采样周期的数字化窗口）。然后将来自每个收发器的输出信号组合以产生每个周期的组合信号。在发射脉冲的数字化窗口内的每个采样周期中的组合信号被平均以产生数字化窗口内的每个采样周期的平均信号。然后将这些平均信号数字化。

17. 发明申请

US20120049972A1 DOWNCONVERSION MIXER 有权
标题翻译： DOWNCONVERSION混合器
公开(公告)号：US20120049972A1
公开(公告)日：2012-03-01
申请号：US12871626
申请日：2010-08-30
申请人： Brian P. Ginsburg , Vijay B. Rentala , Srinath M. Ramaswamy , Baher S. Haroun , Eunyoung Seok
发明人： Brian P. Ginsburg , Vijay B. Rentala , Srinath M. Ramaswamy , Baher S. Haroun , Eunyoung Seok
IPC分类号： H01P1/10 , H01P5/18
CPC分类号： H01P5/184 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/165 , H03D2200/0023
摘要： At very high frequencies, generally above 100 GHz, the performance of traditional radio frequency (RF) circuitry begins to significantly limit performance. An example is the hybrid coupler, which can have a relatively narrow 90° bandwidth in these frequency ranges. Here, however, a branch-line hybrid coupler (which has been integrated into a quadrature downconversion mixer) has been modified. Namely, an adjustable impedance network has been coupled to isolation port (which has traditionally been terminated) to substantially increase the tuning range and expand the bandwidth of the quadrature mixer within these very high frequency ranges.
摘要翻译：在非常高的频率（通常在100GHz以上），传统射频（RF）电路的性能开始显着地限制性能。一个例子是混合耦合器，其在这些频率范围内可以具有相对窄的90°带宽。然而，这里已经修改了分支线路混合耦合器（其已被集成到正交下变频混频器中）。也就是说，可调阻抗网络已经耦合到隔离端口（传统上已被终止），以显着增加调谐范围并且在这些非常高的频率范围内扩大正交混频器的带宽。

18. 发明授权

US07919860B2 Semiconductor device having wafer level chip scale packaging substrate decoupling 有权
标题翻译：具有晶圆级芯片级封装衬底去耦的半导体器件
公开(公告)号：US07919860B2
公开(公告)日：2011-04-05
申请号：US12048294
申请日：2008-03-14
申请人： Rajen M. Murugan , Robert F. McCarthy , Baher S. Haroun , Peter R. Harper
发明人： Rajen M. Murugan , Robert F. McCarthy , Baher S. Haroun , Peter R. Harper
IPC分类号： H01L23/48
CPC分类号： H01L23/3114 , H01L23/5223 , H01L23/525 , H01L24/11 , H01L24/12 , H01L2224/02313 , H01L2224/0401 , H01L2224/0558 , H01L2224/05624 , H01L2224/16 , H01L2924/14 , H01L2924/19041 , H01L2924/19104
摘要： One aspect of the invention provides a semiconductor device that includes a microchip having an outermost surface. First and second bond pads are located on the microchip and near the outermost surface. A first UBM contact is located on the outermost surface and between the first and second bond pads. The first UBM contact is offset from the first bond pad. A second UBM contact is located on the outermost surface and between the first and second bond pads. The second UBM contact is offset from the second bond pad, and a capacitor supported by the microchip is located between the first and second UBM contacts.
摘要翻译：本发明的一个方面提供一种包括具有最外表面的微芯片的半导体器件。第一和第二接合焊盘位于微芯片上并且在最外表面附近。第一UBM触点位于最外表面和第一和第二接合焊盘之间。第一个UBM触点与第一个焊盘相抵消。第二UBM触点位于最外表面上以及第一和第二接合焊盘之间。第二UBM触点偏离第二接合焊盘，并且由微芯片支撑的电容器位于第一和第二UBM触点之间。

19. 发明申请

US20100162061A1 TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS 有权
标题翻译：用于IEEE 1149.1测试访问端口的多个光纤扫描接入的TAP和链接模块
公开(公告)号：US20100162061A1
公开(公告)日：2010-06-24
申请号：US12539373
申请日：2009-08-11
申请人： Baher S. Haroun , Lee D. Whetsel
发明人： Baher S. Haroun , Lee D. Whetsel
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/318536 , G01R31/318544 , G01R31/318555 , G01R31/318558 , G11C29/46
摘要： An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
摘要翻译：描述了用于在集成电路上测试多个电路的架构。该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。

20. 发明授权

US06324662B1 TAP and linking module for scan access of multiple cores with IEEE 1149.1 test access ports 有权
标题翻译： TAP和连接模块，用于具有IEEE 1149.1测试访问端口的多个核心的扫描访问
公开(公告)号：US06324662B1
公开(公告)日：2001-11-27
申请号：US09277504
申请日：1999-03-26
申请人： Baher S. Haroun , Lee D. Whetsel
发明人： Baher S. Haroun , Lee D. Whetsel
IPC分类号： G01R3128
CPC分类号： G01R31/318536 , G01R31/318555 , G01R31/318563
摘要： An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
摘要翻译：描述了用于在集成电路上测试多个电路的架构。该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。

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