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11. 发明申请

US20050185575A1 Asymmetrical mimo wireless communications 有权
标题翻译：不对称mimo无线通信
公开(公告)号：US20050185575A1
公开(公告)日：2005-08-25
申请号：US10979368
申请日：2004-11-01
申请人： Christopher Hansen , Jason Trachewsky , Nambirajan Seshadri , Kelly Cameron , Hau Tran , Ba-Zhong Shen
发明人： Christopher Hansen , Jason Trachewsky , Nambirajan Seshadri , Kelly Cameron , Hau Tran , Ba-Zhong Shen
IPC分类号： H04B7/04 , H04B7/06 , H04B7/08 , H04B7/216 , H04J11/00 , H04M1/00
CPC分类号： H04B7/0613 , H04B7/0413
摘要： A method for asymmetrical MIMO wireless communication begins by determining a number of transmission antennas for the asymmetrical MIMO wireless communication. The method continues by determining a number of reception antennas for the asymmetrical MIMO wireless communication. The method continues by, when the number of transmission antennas exceeds the number of reception antennas, using spatial time block coding for the asymmetrical MIMO wireless communication. The method continues by, when the number of transmission antennas does not exceed the number of reception antennas, using spatial multiplexing for the asymmetrical MIMO wireless communication.
摘要翻译：一种用于非对称MIMO无线通信的方法是通过确定用于非对称MIMO无线通信的多个发送天线来开始的。该方法通过确定用于非对称MIMO无线通信的接收天线的数量来继续。当发送天线的数量超过接收天线的数量时，该方法继续使用用于非对称MIMO无线通信的空间时间块编码。当发送天线的数量不超过接收天线的数量时，该方法继续使用用于非对称MIMO无线通信的空间复用。

12. 发明申请

US20050166132A1 IPHD (iterative parallel hybrid decoding) of various MLC (multi-level code) signals 失效
标题翻译：各种MLC（多级代码）信号的IPHD（迭代并行混合解码）
公开(公告)号：US20050166132A1
公开(公告)日：2005-07-28
申请号：US11017157
申请日：2004-12-20
申请人： Ba-Zhong Shen , Hau Tran , Kelly Cameron
发明人： Ba-Zhong Shen , Hau Tran , Kelly Cameron
IPC分类号： H03M13/11 , H03M13/25 , H03M13/29 , H04L1/00 , H04L27/18 , H03M13/00 , G06F11/00
CPC分类号： H04L1/005 , H03M13/1105 , H03M13/1111 , H03M13/1117 , H03M13/112 , H03M13/1148 , H03M13/255 , H03M13/258 , H03M13/2957 , H03M13/6325 , H03M13/658 , H04L1/0058 , H04L1/0071 , H04L27/18
摘要： IPHD (Iterative Parallel Hybrid Decoding) of various MLC (Multi-Level Code) signals. Various embodiments are provided by which IPHD may be performed on MLC LDPC (Multi-Level Code Low Density Parity Check) coded modulation signals mapped using a plurality of mappings. This IPHD may also be performed on MLC LDPC coded modulation signals mapped using only a singe mapping as well. In addition, various embodiments are provided by which IPHD may be performed on ML TC (Multi-Level Turbo Code) signals. These principles of IPHD, shown with respect to various embodiments IPHD of MLC LDPC coded modulation signals as well as the IPHD of ML TC signals, may be extended to performing IPHD of other signal types as well. Generally speaking, based on the degree of the MLC signal, a corresponding number of parallel paths operate in cooperation to decode the various levels of the MLC signal.
摘要翻译：各种MLC（多级码）信号的IPHD（迭代并行混合解码）。提供了各种实施例，通过该实施例可以对使用多个映射映射的MLC LDPC（多级码低密度奇偶校验）编码的调制信号执行IPHD。也可以对仅使用单个映射映射的MLC LDPC编码调制信号执行该IPHD。此外，提供了可以在ML TC（多级Turbo码）信号上执行IPHD的各种实施例。关于各种实施方案所示的IPHD的这些原理，MLC LDPC编码调制信号以及ML TC信号的IPHD也可以扩展到执行其他信号类型的IPHD。一般而言，基于MLC信号的程度，相应数量的并行路径协同工作来解码MLC信号的各种级别。

13. 发明申请

US20080043878A1 Parallel concatenated code with soft-in soft-out interactive turbo decoder 有权
公开(公告)号：US20080043878A1
公开(公告)日：2008-02-21
申请号：US11728519
申请日：2007-03-26
申请人： Kelly Cameron , Ba-Zhong Shen , Hau Tran , Christopher Jones , Thomas Hughes
发明人： Kelly Cameron , Ba-Zhong Shen , Hau Tran , Christopher Jones , Thomas Hughes
IPC分类号： H04L27/04
CPC分类号： H03M13/3972 , H03M13/151 , H03M13/1515 , H03M13/25 , H03M13/258 , H03M13/27 , H03M13/2757 , H03M13/29 , H03M13/2966 , H03M13/2978 , H03M13/3905 , H03M13/3922 , H03M13/3927 , H03M13/3988 , H03M13/4107 , H03M13/6505 , H03M13/6561 , H04L1/0041 , H04L1/005 , H04L1/006 , H04L1/0065 , H04L1/0066 , H04L1/0068 , H04L1/0071
摘要： A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

14. 发明申请

US20070016841A1 Variable code rate and signal constellation turbo trellis coded modulation codec 有权
标题翻译：可变码率和信号星座turbo网格编码调制编解码器
公开(公告)号：US20070016841A1
公开(公告)日：2007-01-18
申请号：US11491729
申请日：2006-07-24
申请人： Kelly Cameron , Ba-Zhong Shen , Hau Tran
发明人： Kelly Cameron , Ba-Zhong Shen , Hau Tran
IPC分类号： H03M13/00
CPC分类号： H04L1/005 , G11B20/18 , H03M13/1102 , H03M13/256 , H03M13/258 , H03M13/27 , H03M13/2767 , H03M13/2771 , H03M13/2785 , H03M13/2957 , H03M13/4123 , H03M13/4161 , H03M13/45 , H04L1/0041 , H04L1/006 , H04L1/0066 , H04L1/0068 , H04L1/0071
摘要： Variable code rate and signal constellation turbo trellis coded modulation (TTCM) codec. A common trellis is employed at both ends of a communication system (in an encoder and decoder) to code and decode data at different rates. The encoding employs a single TTCM encoder whose output bits may be selectively punctured to support multiple modulations (constellations and mappings) according to a rate control sequence. A single TTCM decoder is operable to decode each of the various rates at which the data is encoded by the TTCM encoder. The rate control sequence may include a number of rate controls arranged in a period that is repeated during encoding and decoding. Either one or both of the encoder and decoder may adaptively select a new rate control sequence based on operating conditions of the communication system, such as a change in signal to noise ratio (SNR).
摘要翻译：可变码率和信号星座turbo网格编码调制（TTCM）编解码器。在通信系统（编码器和解码器）的两端采用通用网格，以不同速率对数据进行编码和解码。该编码采用单个TTCM编码器，其输出位可以根据速率控制序列被选择性地打孔以支持多种调制（星座和映射）。单个TTCM解码器可操作以解码由TTCM编码器编码数据的各种速率的每一个。速率控制序列可以包括在编码和解码期间重复的周期中布置的速率控制的数量。编码器和解码器中的一个或两者可以基于通信系统的操作条件（诸如信噪比（SNR）的变化）来自适应地选择新的速率控制序列。

15. 发明申请

US20060251184A1 Parallel concatenated code with soft-in-soft-out interactive turbo decoder 失效
标题翻译：软和软交互式turbo解码器的并行级联代码
公开(公告)号：US20060251184A1
公开(公告)日：2006-11-09
申请号：US11481365
申请日：2006-07-05
申请人： Kelly Cameron , Ba-Zhong Shen , Hau Tran , Christopher Jones , Thomas Hughes
发明人： Kelly Cameron , Ba-Zhong Shen , Hau Tran , Christopher Jones , Thomas Hughes
IPC分类号： H04L27/00 , H04L23/02
CPC分类号： H03M13/3972 , H03M13/151 , H03M13/1515 , H03M13/25 , H03M13/258 , H03M13/27 , H03M13/2757 , H03M13/29 , H03M13/2966 , H03M13/2978 , H03M13/3905 , H03M13/3922 , H03M13/3927 , H03M13/3988 , H03M13/4107 , H03M13/6505 , H03M13/6561 , H04L1/0041 , H04L1/005 , H04L1/006 , H04L1/0065 , H04L1/0066 , H04L1/0068 , H04L1/0071
摘要： A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.
摘要翻译：一种并行级联（Turbo）编码和解码的方法。 Turbo编码器接收一系列输入数据元组并进行编码。输入序列可以对应于原始数据源的序列，或者对应于已由Reed-Solomon编码器提供的已经编码的数据序列。 turbo编码器通常包括由一个或多个交织器分离的两个或更多个编码器。输入数据元组可以使用其中交织根据某些方法（例如块或随机交织）的加法规则进行交织，其中输入元组可以只交织到具有相同模N的交织位置其中N是整数），因为它们在输入数据序列中具有。如果所有的输入元组都是由所有的编码器编码的，那么输出元组可以从编码器顺序选择，也不会丢失元组。如果输入元组包含多个比特，那么这些比特可以与具有相同模N和相同比特位置的交织位置独立交织。这可以提高代码的鲁棒性。第一编码器可以不具有交织器，或者所有编码器可以具有交织器，无论输入元组位是否独立交错。模式类型交织也允许并行解码。

16. 发明申请

US20050262424A1 Efficient design to implement LDPC (Low Density Parity Check) decoder 有权
标题翻译：高效设计实现LDPC（低密度奇偶校验）解码器
公开(公告)号：US20050262424A1
公开(公告)日：2005-11-24
申请号：US11171998
申请日：2005-06-30
申请人： Hau Tran , Kelly Cameron , Ba-Zhong Shen
发明人： Hau Tran , Kelly Cameron , Ba-Zhong Shen
IPC分类号： G06F11/00 , H03M13/00 , H03M13/11
CPC分类号： H03M13/255 , H03M13/1102 , H03M13/1111 , H03M13/1117 , H03M13/112 , H03M13/1134 , H03M13/1137 , H03M13/116 , H03M13/1165 , H03M13/6505 , H03M13/658
摘要： Efficient design to implement LDPC decoder. The efficient design presented herein provides for a solution that is much easier, smaller, and has less complexity than other possible solutions. The use of a ping-pong memory structure (or pseudo-dual port memory structure) in conjunction with a metric generator near the decoder's front end allows parallel bit/check node processing. An intelligently operating barrel shifter operates with a message passing memory that is operable to store updated edges messages with respect to check nodes as well as updated edges messages with respect to bit nodes. Using an efficient addressing scheme allows the same memory structure to store the two types of edges messages with respect to bit nodes: (1) corresponding to information bits and (2) corresponding to parity bits. In addition, an intelligently designed hardware macro block may be instantiated a number of times into the decoder design to support ever greater design efficiency.
摘要翻译：高效设计实现LDPC解码器。本文提供的高效设计提供了一种比其他可能的解决方案更简单，更小，复杂度更低的解决方案。与解码器前端附近的度量发生器结合使用乒乓存储器结构（或伪双端口存储器结构）允许并行位/校验节点处理。智能操作的桶形移位器利用消息传递存储器操作，该存储器可操作以存储相对于校验节点的更新的边缘消息以及相对于位节点的更新的边缘消息。使用有效的寻址方案允许相同的存储器结构相对于比特节点存储两种类型的边缘消息：（1）对应于信息比特和（2）对应于奇偶校验位。此外，智能设计的硬件宏块可以被多次实例化到解码器设计中以支持更大的设计效率。

17. 发明申请

US20050262408A1 Fast min* - or max* - circuit in LDPC (Low Density Parity Check) decoder 失效
标题翻译： LDPC（低密度奇偶校验）解码器中的快速最小*或最大*电路
公开(公告)号：US20050262408A1
公开(公告)日：2005-11-24
申请号：US11172329
申请日：2005-06-30
申请人： Hau Tran , Kelly Cameron , Ba-Zhong Shen
发明人： Hau Tran , Kelly Cameron , Ba-Zhong Shen
IPC分类号： G01R31/28 , H03M13/11 , H03M13/25 , H04L1/00
CPC分类号： H03M13/112 , H03M13/1105 , H03M13/1117 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2906 , H03M13/6583 , H04L1/0003 , H04L1/0057
摘要： Fast min*− (min-star-minus) or max*− (max-star-minus) circuit in LDPC (Low Density Parity Check) decoder. A novel and efficient approach by which certain of the calculations required to perform check node processing within various types of decoders is presented. The functionality and architectures presented herein are applicable to LDPC decoders and may also be employed within other types of decoders that are operable to decode other types of coded signals as well. The parallel and sometimes simultaneous calculation and determination of certain parts of the overall resultant of the max*− and/or min*− processing allows for very fast operation when compared to prior art approaches.
摘要翻译： LDPC（低密度奇偶校验）解码器中的快速min * - （min-star-minus）或max * - （max-star-minus）电路。提出了一种新颖有效的方法，通过该方法可以在各种类型的解码器中执行校验节点处理所需的某些计算。这里呈现的功能和体系结构可应用于LDPC解码器，并且还可以用于可操作以解码其他类型的编码信号的其他类型的解码器。与现有技术方法相比，最大*和/或最小*处理的总体结果的某些部分的并行和有时同时的计算和确定允许非常快速的操作。

18. 发明申请

US20050246606A1 Decoding LDPC (Low Density Parity Check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph 失效
标题翻译：使用二分图两边乘法（或对数域加法）对LDPC（低密度奇偶校验）码进行解码
公开(公告)号：US20050246606A1
公开(公告)日：2005-11-03
申请号：US10865556
申请日：2004-06-10
申请人： Kelly Cameron , Ba-Zhong Shen , Hau Tran
发明人： Kelly Cameron , Ba-Zhong Shen , Hau Tran
IPC分类号： H03M13/11 , H03M13/00
CPC分类号： H03M13/1125 , H03M13/1111 , H03M13/1117 , H03M13/112 , H03M13/1134 , H03M13/255 , H03M13/6583
摘要： Decoding LDPC (Low Density Parity Check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph. A novel approach of decoding LDPC coded signals is presented whereby edge messages may be updated using only multiplication (or log domain addition). By appropriate modification of the various calculations that need to be performed when updating edge messages, the calculations may be reduced to only performing product of terms functions. When implementing such functionality in hardware within a communication device that is operable to decode LDPC coded signals, this reduction in processing complexity greatly eases the actual hardware's complexity as well. A significant savings in processing resources, memory, memory management concerns, and other performance driving parameters may be made.
摘要翻译：使用二分图两边的乘法（或对数域中的加法）解码LDPC（低密度奇偶校验）码和图。提出了一种解码LDPC编码信号的新颖方法，其中可以仅使用乘法（或对数域加法）来更新边缘消息。通过适当修改在更新边缘消息时需要执行的各种计算，可以将计算减少到仅执行术语函数的乘积。当在可操作来解码LDPC编码信号的通信设备中的硬件中实现这种功能时，处理复杂度的这种降低也极大地减轻了实际硬件的复杂性。可以显着节省处理资源，存储器，存储器管理问题和其他性能驱动参数。

19. 发明申请

US20050015705A1 Parallel concatenated code with soft-in soft-out interactive turbo decoder 有权
标题翻译：并行级联代码与软入软交互式turbo解码器
公开(公告)号：US20050015705A1
公开(公告)日：2005-01-20
申请号：US10843606
申请日：2004-05-11
申请人： Kelly Cameron , Ba-Zhong Shen , Hau Tran , Christopher Jones , Thomas Hughes
发明人： Kelly Cameron , Ba-Zhong Shen , Hau Tran , Christopher Jones , Thomas Hughes
IPC分类号： H03M13/15 , H03M13/25 , H03M13/27 , H03M13/29 , H03M13/41 , H03M13/45 , H04L1/00 , G06F11/00 , H03M13/03
CPC分类号： H03M13/3972 , H03M13/151 , H03M13/1515 , H03M13/25 , H03M13/258 , H03M13/27 , H03M13/2757 , H03M13/29 , H03M13/2966 , H03M13/2978 , H03M13/3905 , H03M13/3922 , H03M13/3927 , H03M13/3988 , H03M13/4107 , H03M13/6505 , H03M13/6561 , H04L1/0041 , H04L1/005 , H04L1/006 , H04L1/0065 , H04L1/0066 , H04L1/0068 , H04L1/0071
摘要： A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Soloman encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.
摘要翻译：一种并行级联（Turbo）编码和解码的方法。 Turbo编码器接收一系列输入数据元组并进行编码。输入序列可以对应于原始数据源的序列，或者对应于已经编码的数据序列，例如由Reed-Soloman编码器提供的。 turbo编码器通常包括由一个或多个交织器分离的两个或更多个编码器。输入数据元组可以使用其中交织根据某些方法（例如块或随机交织）的加法规则进行交织，其中输入元组可以只交织到具有相同模N的交织位置其中N是整数），因为它们在输入数据序列中具有。如果所有的输入元组都是由所有的编码器编码的，那么输出元组可以从编码器顺序选择，也不会丢失元组。如果输入元组包含多个比特，那么这些比特可以与具有相同模N和相同比特位置的交织位置独立交织。这可以提高代码的鲁棒性。第一编码器可以不具有交织器，或者所有编码器可以具有交织器，无论输入元组位是否独立交错。模式类型交织也允许并行解码。

20. 发明申请

US20050010856A1 Low density parity check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses 有权
标题翻译：使用min *，min **，max *或max **的低密度奇偶校验（LDPC）码解码器及其各自的反转
公开(公告)号：US20050010856A1
公开(公告)日：2005-01-13
申请号：US10901528
申请日：2004-07-29
申请人： Ba-Zhong Shen , Kelly Cameron , Hau Tran
发明人： Ba-Zhong Shen , Kelly Cameron , Hau Tran
IPC分类号： H04L1/00 , G06F11/00 , H03M13/00
CPC分类号： H04L1/005 , H04L1/0057
摘要： Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.
摘要翻译：使用min *，min **，max *或max **的低密度奇偶校验（LDPC）码解码器及其各自的反转。首次演示了用于解码LDPC编码信号的min *处理。另外，当执行执行使用LDPC码编码的信号的解码所需的计算时，也可以采用max *，min **或max **（及其各自的反转）。当解码涉及从多个可能值中确定最小和/或最大值或最小和/或最大对数校正值时，可以采用这些新参数来为LDPC码提供大大改进的解码处理。采用本文所述的最小*，最大*，最小**或最大**（及其相应的反转）解码处理，在LDPC编码信号的解码中采用的处理步骤的总数显着减少。

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