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11. 发明授权

US06434080B1 Semiconductor memory and method of controlling the same 失效
标题翻译：半导体存储器及其控制方法
公开(公告)号：US06434080B1
公开(公告)日：2002-08-13
申请号：US09707845
申请日：2000-11-08
申请人： Hitoshi Shiga
发明人： Hitoshi Shiga
IPC分类号： G11C800
CPC分类号： G11C16/3445 , G11C5/145 , G11C8/08 , G11C16/12 , G11C16/30 , G11C16/3459
摘要： A semiconductor memory has a memory cell array, a boosted voltage generator to generate a boosted voltage and a decoder to select memory cells in said memory cell array in response to an address signal. The voltage generator is activated in response to input of a first command, and kept active for a period of repeated input of a second command to control for the voltage generator, following the first command. The semiconductor memory may be provided with a regular operation mode in which the voltage generator is controlled to be in an active or inactive state by means of a first command signal in response to a predetermined signal, and a successive operation mode in which the voltage generator is kept active by a second command signal in response to another predetermined signal.
摘要翻译：半导体存储器具有存储单元阵列，用于产生升压电压的升压电压发生器和解码器，以响应于地址信号选择所述存储单元阵列中的存储单元。电压发生器响应于第一命令的输入被激活，并且在第一命令之后保持有效的第二命令的重复输入的周期以控制电压发生器。半导体存储器可以被提供有常规操作模式，其中电压发生器通过响应于预定信号的第一命令信号被控制为处于活动或非活动状态，以及连续操作模式，其中电压发生器响应于另一个预定信号由第二命令信号保持活动。

12. 发明授权

US06240019B1 Non-volatile semiconductor memory device having a function for controlling the range of distribution of memory cell threshold voltages 失效
标题翻译：具有用于控制存储单元阈值电压的分布范围的功能的非易失性半导体存储器件
公开(公告)号：US06240019B1
公开(公告)日：2001-05-29
申请号：US09471489
申请日：1999-12-23
申请人： Hitoshi Shiga , Toru Tanzawa , Masanobu Saito
发明人： Hitoshi Shiga , Toru Tanzawa , Masanobu Saito
IPC分类号： G11C1606
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404 , G11C2216/20
摘要： A non-volatile semiconductor memory device according to the invention comprises a memory cell array having a plurality of non-volatile memory cells, and a write state machine controlling a voltage applied to a memory cell selected from the memory cell array and a voltage application period, in accordance with each of reading of data from the selected memory cell, writing of data into the selected memory cell, and erasion of data from the selected memory. The write state machine executes writing, under a first writing condition, on a predetermined number of memory cells included in the memory cell array, and executes writing on memory cells other than the predetermined number of memory cells, under a second writing condition set in accordance with a result of the writing executed under the first writing condition.
摘要翻译：根据本发明的非易失性半导体存储器件包括具有多个非易失性存储单元的存储单元阵列，以及控制施加到从存储单元阵列选择的存储单元的电压的写状态机和施加电压的周期根据从所选择的存储器单元读取数据的每一个，将数据写入所选存储单元，以及从所选存储器中擦除数据。写入状态机在第一写入条件下执行包含在存储单元阵列中的预定数量的存储单元上的写入，并且在按照相应设置的第二写入条件下执行对除了预定数量的存储单元之外的存储单元的写入其结果是在第一写入条件下执行写入。

13. 发明授权

US08331158B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08331158B2
公开(公告)日：2012-12-11
申请号：US13016286
申请日：2011-01-28
申请人： Hitoshi Shiga
发明人： Hitoshi Shiga
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06 , G11C5/14
CPC分类号： G11C16/10 , G11C16/0483
摘要： In writing operation, charge pumps of a memory apply any of first to n-th voltages which are different from each other. An application-voltage selector selects voltages to be applied to WLs among the first to n-th voltages. A word-line number register stores the number of WLs to which each of the first to n-th voltages is to be applied for the first to n-th voltages. A storage stores a correspondence table that stores a relationship between the number of WLs for each of the first to n-th voltages and the number of charge pumps allocated to the first to n-th voltages. A generation-voltage selector allocates charge pumps to generate the first to n-th voltages based on the correspondence table according to the number of WLs for each of the first to n-th voltages. Each charge pump generates any of the first to n-th voltages allocated by the generation-voltage selector.
摘要翻译：在写入操作时，存储器的电荷泵应用彼此不同的第一至第n电压中的任何一个。应用电压选择器选择在第一至第n电压中施加到WL的电压。字线号寄存器存储要施加第一至第n电压的第一至第n电压中的每一个的WL的数量。存储器存储存储第一至第n电压中的每一个的WL的数量与分配给第一至第n电压的电荷泵的数量之间的关系的对应表。发电电压选择器基于与第一至第n电压中的每一个相关的WL的数量的对应表，分配电荷泵以产生第一至第n电压。每个电荷泵产生由发电电压选择器分配的第一至第n电压中的任一个。

14. 发明授权

US08331147B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US08331147B2
公开(公告)日：2012-12-11
申请号：US12838811
申请日：2010-07-19
申请人： Hitoshi Shiga
发明人： Hitoshi Shiga
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/3436
摘要： A nonvolatile semiconductor memory device comprises: a memory cell array configured by a plurality of first and second lines and a plurality of memory cells, each of the memory cells being selected by the first and second lines and being configured to store multiple-bit data in a nonvolatile manner; a data bus configured to transmit write data to be written to the plurality of memory cells, the write data being configured by a plurality of unit data; a column selection unit configured by a plurality of data latches, each of the data latches being configured to directly receive the unit data inputted from the data bus and to retain the unit data; and a control unit configured to control activation/non-activation of the data latches. During a programming operation, for each unit data inputted to the column selection unit, the control unit activates one of the data latches corresponding to a certain one of the memory cells where the unit data is to be stored.
摘要翻译：非易失性半导体存储器件包括：由多个第一和第二线路以及多个存储器单元配置的存储器单元阵列，每个存储单元由第一和第二线路选择，并被配置为存储多位数据非挥发性; 数据总线，被配置为发送要写入到所述多个存储器单元的写入数据，所述写入数据由多个单位数据配置; 由多个数据锁存器配置的列选择单元，每个数据锁存器被配置为直接接收从数据总线输入的单元数据并保持单元数据; 以及控制单元，被配置为控制数据锁存器的激活/非激活。在编程操作期间，对于输入到列选择单元的每个单元数据，控制单元激活对应于要存储单元数据的存储单元中的某一个存储单元的数据锁存器之一。

15. 发明授权

US08327063B2 Memory system with a semiconductor memory device 有权
标题翻译：具有半导体存储器件的存储器系统
公开(公告)号：US08327063B2
公开(公告)日：2012-12-04
申请号：US12405754
申请日：2009-03-17
申请人： Hitoshi Shiga , Hidetaka Tsuji
发明人： Hitoshi Shiga , Hidetaka Tsuji
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： A memory system with a semiconductor memory device, in which a physical block of n-bits serves as an erase unit, wherein the address management of the memory device is performed by a logical block with m-bits, “m” being larger than “n” and expressed by a power of two, and wherein a n-bit portion continued from the head address in the logical block is defined as a first management unit corresponding to one physical block of the memory device, and a number of the remaining fraction portions each defined as a second management unit are gathered so as to correspond to one physical block of the memory device.
摘要翻译：一种具有半导体存储器件的存储器系统，其中n位的物理块用作擦除单元，其中存储器件的地址管理由具有m位的逻辑块执行，m大于n并表示通过2的幂，并且其中从逻辑块中的头地址继续的n位部分被定义为对应于存储器件的一个物理块的第一管理单元，并且其余的分数部分的数量被定义为收集第二管理单元以对应于存储器件的一个物理块。

16. 发明授权

US07650584B2 Application specific semiconductor integrated circuit and its manufacturing method thereof 失效
标题翻译：专用半导体集成电路及其制造方法
公开(公告)号：US07650584B2
公开(公告)日：2010-01-19
申请号：US11838605
申请日：2007-08-14
申请人： Hitoshi Shiga , Kiyofumi Sakurai , Kenji Mima
发明人： Hitoshi Shiga , Kiyofumi Sakurai , Kenji Mima
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5077 , G11C5/025 , H01L27/0207 , H01L27/11898
摘要： An ASIC includes a first-wire extended in a first-direction and a second-wire extended in a parallel direction to the first-wire and both are placed on a first-wire layer; and a third-wire placed on a second-wire layer above the first-wire layer and is extended above the wire and above the second-wire in a second-direction which intersects the first-direction and passing through a first via-hole is connected to the first-wire, and a fourth-wire separated from the third-wire extended in a parallel direction above the first-wire and above the second-wire and a fifth-wire separated from both the third-wire and the fourth-wire and extended in a parallel direction in a smallest space and passing through a second via-hole is connected to the second-wire, wherein, one end of the fifth-wire is extended to the center between the second-wire and the first-wire from above the second-wire.
摘要翻译： ASIC包括沿第一方向延伸的第一线和与第一线并联延伸的第二线，并且两者均放置在第一线层上; 以及放置在所述第一线层上方的二线层上并且在所述线的上方延伸并且在与所述第一方向相交并穿过第一通孔的第二方向上方的所述第二线上的第三线是连接到第一线，以及与第三线分离的第四线，该第三线在第一线上方平行并且在第二线上方延伸，以及与第三线和第四线分离的第五线，并且在最小的空间中沿平行方向延伸并穿过第二通孔的第二线连接到第二线，其中，第五线的一端延伸到第二线和第一线之间的中心，电线从二线以上。

17. 发明申请

US20080043531A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20080043531A1
公开(公告)日：2008-02-21
申请号：US11849891
申请日：2007-09-04
申请人： Yasushi KAMEDA , Ken Takeuchi , Hitoshi Shiga , Takuya Futatsuyama , Koichi Kawai
发明人： Yasushi KAMEDA , Ken Takeuchi , Hitoshi Shiga , Takuya Futatsuyama , Koichi Kawai
IPC分类号： G11C16/06
CPC分类号： G11C16/102
摘要： The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.
摘要翻译：非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持电路工作。然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。同时，将数据输出到奇数位线，并且确定奇数位线的电位。然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。

18. 发明授权

US07193896B2 Multi-value semiconductor memory device and method capable of caching a lower page data upon an incomplete write of an upper page data 有权
标题翻译：多值半导体存储器件和方法能够在不完整的上位页数据写入时缓存下页数据
公开(公告)号：US07193896B2
公开(公告)日：2007-03-20
申请号：US11167301
申请日：2005-06-28
申请人： Hitoshi Shiga
发明人： Hitoshi Shiga
IPC分类号： G11C29/04 , G11C16/06
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/0483 , G11C2207/2245 , G11C2211/5646
摘要： A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged to store multi-value data; a sense amplifier circuit configured to read data of and write data in the memory cell array; and a controller configured to control data read and write of the memory cell array, wherein the controller has such a function as, when an upper page data write sequence ends in failure, the upper page data being one to be written into an area of the memory cell array where lower page data has already been written, to cache the lower page data read out of the memory cell array and held in the sense amplifier circuit.
摘要翻译：半导体存储器件包括：存储单元阵列，其中电可重写和非易失性存储器单元被布置为存储多值数据; 读出放大器电路，被配置为读取存储单元阵列中的数据并写入数据; 以及控制器，其被配置为控制所述存储单元阵列的数据读取和写入，其中所述控制器具有如下功能：当上页数据写入序列以故障结束时，所述上页数据为要写入所述存储单元阵列的区域中的一个存储单元阵列，其中已经写入较低页数据，以缓存从存储单元阵列读出并保持在读出放大器电路中的下部页数据。

19. 发明申请

US20050135157A1 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050135157A1
公开(公告)日：2005-06-23
申请号：US10957826
申请日：2004-10-05
申请人： Hitoshi Shiga
发明人： Hitoshi Shiga
IPC分类号： G11C16/02 , G11C16/00 , G11C16/04 , G11C16/06 , G11C16/14 , G11C16/34
CPC分类号： G11C16/344 , G11C16/0483
摘要： A semiconductor memory device including: a cell array with electrically rewritable and non-volatile memory cells arranged therein; a sense amplifier circuit configured to read data of and write data into the cell array; and a controller configured to control read, write and erase of the cell array, wherein the controller executes an erase sequence for erasing a selected block in the cell array in response to erase command and address input in such a way of: executing a first erase-verify operation for verifying an erase state of the selected block; ending the erase sequence if the erase state of the selected block has been verified by the first erase-verify operation; whereas executing an erase operation for the selected block if the erase state has not been verified.
摘要翻译：一种半导体存储器件，包括：具有布置在其中的电可重写和非易失性存储单元的单元阵列; 读出放大器电路，被配置为读取数据并将数据写入单元阵列; 以及控制器，其被配置为控制所述单元阵列的读取，写入和擦除，其中所述控制器响应于擦除命令和地址输入执行用于擦除所述单元阵列中的所选块的擦除序列，其方式为：执行第一擦除 - 验证所选块的擦除状态的操作; 如果所选块的擦除状态已被第一次擦除验证操作验证，则结束擦除序列; 而如果擦除状态尚未被验证，则对所选择的块执行擦除操作。

20. 发明授权

US06795352B2 Nonvolatile semiconductor memory having page mode with a plurality of banks 失效
标题翻译：具有多个存储体的页面模式的非易失性半导体存储器
公开(公告)号：US06795352B2
公开(公告)日：2004-09-21
申请号：US10703005
申请日：2003-11-05
申请人： Toru Tanzawa , Shigeru Atsumi , Akira Umezawa , Tadayuki Taura , Hitoshi Shiga , Yoshinori Takano
发明人： Toru Tanzawa , Shigeru Atsumi , Akira Umezawa , Tadayuki Taura , Hitoshi Shiga , Yoshinori Takano
IPC分类号： G11C1604
CPC分类号： G11C16/0408 , G11C16/08 , G11C16/26 , G11C29/70
摘要： The semiconductor memory comprises a reference current generator, first and second current converters, sense amplifiers for read, and sense amplifiers for verify. The reference current generator generates a first voltage dependent upon the current flowing through a reference cell. The first current converters, to which the first voltage is input, each generate a second voltage. The second current converters, to which the first voltage is input, each generate a third voltage. The sense amplifiers for read output data of a selection memory cell, comparing the voltage of the data-line for read with the second voltage. The sense amplifiers for verify output verify data of the selection memory cell, comparing the voltage of the data-lines for verify and the third voltage.
摘要翻译：半导体存储器包括参考电流发生器，第一和第二电流转换器，用于读出的读出放大器和用于验证的读出放大器。参考电流发生器根据流过参考单元的电流产生第一电压。输入第一电压的第一电流转换器各自产生第二电压。第一电压输入的第二电流转换器各自产生第三电压。读出放大器，用于选择存储器单元的读取输出数据，将用于读取的数据线的电压与第二电压进行比较。用于验证输出的读出放大器验证选择存储单元的数据，比较用于验证的数据线的电压和第三电压。

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