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11. 发明授权

US6159789A Method for fabricating capacitor 失效
标题翻译：制造电容器的方法
公开(公告)号：US6159789A
公开(公告)日：2000-12-12
申请号：US306093
申请日：1999-05-06
申请人： Shu-Ya Chuang , Anchor Chen
发明人： Shu-Ya Chuang , Anchor Chen
IPC分类号： H01L21/8242
CPC分类号： H01L27/10876 , H01L27/10852 , H01L27/10885
摘要： A method for fabricating a capacitor in DRAM. A horizontal buried doped region is formed in a substrate. A pad oxide layer and a mask layer are formed in sequence on the substrate. A plurality of first trenches is formed in the substrate. Thus, a plurality of bit lines is formed in the substrate. A plurality of second trenches is formed in the substrate to expose the surface of the bit lines, wherein the second trenches cross the first trenches. Thus, a plurality of silicon islands on the bit lines is formed. A first insulation layer is formed in the first trenches and the second trenches, wherein the sidewall of the silicon islands are partly exposed and doped regions are formed in the exposed sidewall. A gate oxide layer is formed on the sidewall of the silicon islands. A spacer is formed on the gate oxide layer. A second insulation layer is formed over the substrate. The mask layer and the pad oxide layer are removed to expose the top surfaces of the silicon islands. A patterned conductive layer is formed over the substrate. A dielectric layer and an upper electrode are formed in sequence over the substrate.
摘要翻译：一种在DRAM中制造电容器的方法。在衬底中形成水平掩埋掺杂区域。在衬底上依次形成衬垫氧化物层和掩模层。在基板中形成多个第一沟槽。因此，在基板中形成多个位线。在衬底中形成多个第二沟槽以暴露位线的表面，其中第二沟槽穿过第一沟槽。因此，形成位线上的多个硅岛。第一绝缘层形成在第一沟槽和第二沟槽中，其中硅岛的侧壁部分地暴露，并且在暴露的侧壁中形成掺杂区域。在硅岛的侧壁上形成栅氧化层。在栅极氧化层上形成间隔物。在衬底上形成第二绝缘层。去除掩模层和焊盘氧化物层以露出硅岛的顶表面。在衬底上形成图案化的导电层。电介质层和上电极依次形成在衬底上。

12. 发明授权

US6037234A Method of fabricating capacitor 失效
标题翻译：制造电容器的方法
公开(公告)号：US6037234A
公开(公告)日：2000-03-14
申请号：US23879
申请日：1998-02-13
申请人： Gary Hong , Anchor Chen
发明人： Gary Hong , Anchor Chen
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L21/20 , H01L21/28 , H01L21/44
CPC分类号： H01L27/10852 , H01L28/91 , H01L21/76807
摘要： A method of fabricating a capacitor in a DRAM. A semiconductor substrate having a metal-oxide-semiconductor is provided. Using only one photolithography process, a bottom electrode is formed. By forming a dielectric layer over the substrate, and a poly-silicon layer on the dielectric layer, a capacitor is formed.
摘要翻译：一种在DRAM中制造电容器的方法。提供具有金属氧化物半导体的半导体衬底。仅使用一个光刻工艺，形成底部电极。通过在基板上形成电介质层，在电介质层上形成多晶硅层，形成电容器。

13. 发明授权

US5867362A Storage capacitor for DRAM memory cell 失效
标题翻译：用于DRAM存储单元的存储电容器
公开(公告)号：US5867362A
公开(公告)日：1999-02-02
申请号：US928334
申请日：1997-09-12
申请人： Anchor Chen
发明人： Anchor Chen
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/108 , H01G4/06 , H01L21/108
CPC分类号： H01L28/92
摘要： A storage capacitor structural configuration for memory cell units of DRAM devices and a process for constructing the capacitor. The capacitor includes a first electrode and a second electrode that are each electrically conducting layers, and a storage dielectric that is a dielectric layer sandwiched between the two electrodes. The silicon substrate of the device has formed thereon a field oxide layer and a transistor including a gate and a pair of source/drain regions. A first dielectric layer covers the transistor and includes a contact opening over one of the source/drain regions. The first electrode includes a first electrically conducting layer formed inside the contact opening and covering the revealed surface of the source/drain region and the first dielectric layer. A second electrically conducting layer having a rugged surface is formed on the surface of the first electrically conducting layer. A number of deep grooves are formed in the second and first electrically conducting layers, forming a grid-like configuration. The storage dielectric includes a second dielectric layer covering the surface of the grid-like configuration of the second and first electrically conducting layers. The second electrode includes a third electrically conducting layer that covers the surface of the storage dielectric.
摘要翻译：用于DRAM器件的存储单元单元的存储电容器结构配置和用于构造电容器的工艺。电容器包括每个导电层的第一电极和第二电极，以及夹在两个电极之间的电介质层的存储电介质。器件的硅衬底上形成有场氧化物层和包括栅极和一对源极/漏极区域的晶体管。第一电介质层覆盖晶体管并且包括在源/漏区之一上的接触开口。第一电极包括形成在接触开口内部并覆盖源/漏区和第一介电层的露出表面的第一导电层。具有凹凸表面的第二导电层形成在第一导电层的表面上。在第二导电层和第一导电层中形成许多深沟槽，形成网格状构造。存储电介质包括覆盖第二和第一导电层的格栅状构造的表面的第二介电层。第二电极包括覆盖存储电介质的表面的第三导电层。

14. 发明授权

US5736441A High-capacitance dynamic random access memory cell and method for fabricating the same 失效
标题翻译：高电容动态随机存取存储单元及其制造方法
公开(公告)号：US5736441A
公开(公告)日：1998-04-07
申请号：US616960
申请日：1996-03-15
申请人： Anchor Chen
发明人： Anchor Chen
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808
摘要： A semiconductor structure for a DRAM cell having a high capacitance capacitor. The DRAM cell includes a silicon substrate on which a field oxide layer and a transistor having a gate layer and a source/drain region are formed. A contact surface is formed on a surface of the source/drain region. A silicon nitride layer is formed over the gate layer. A thick oxide layer is formed over one part of the silicon nitride layer, at a lateral side of the contact surface. Silicon nitride spacers are formed over opposite lateral sides of the gate layer, the silicon nitride layer, and the thick oxide layer. One of the silicon nitride spacers located adjacent to the contact surface, is shaped in the form of a pointed protrusion. A self-aligned contact insulating layer covers the thick oxide layer and the other silicon nitride spacer, that is located away from the contact surface. This structure defines a jagged surface over at least the contact surface, the pointed protrusion and the silicon nitride layer. A high surface area capacitor structure, including a first conductive layer, a dielectric layer over the first conductive layer, and a second conductive layer over the dielectric layer, is then formed over the jagged surface.
摘要翻译：一种具有高电容电容器的DRAM单元的半导体结构。 DRAM单元包括其上形成有场氧化物层和具有栅极层和源极/漏极区的晶体管的硅衬底。在源极/漏极区域的表面上形成接触表面。在栅极层上形成氮化硅层。在接触表面的侧面，在氮化硅层的一部分上形成厚的氧化物层。氮化硅间隔物形成在栅极层，氮化硅层和厚氧化物层的相对侧面上。位于与接触表面相邻的氮化硅间隔物中的一个被成形为尖突起的形式。自对准接触绝缘层覆盖远离接触表面的厚氧化物层和另一个氮化硅间隔物。该结构限定至少在接触表面，尖突起和氮化硅层上的锯齿状表面。然后在锯齿状表面上形成包括第一导电层，第一导电层上的电介质层和介电层上的第二导电层的高表面积电容器结构。

15. 发明授权

US5523542A Method for making dynamic random access memory cell capacitor 失效
标题翻译：制造动态随机存储单元电容器的方法
公开(公告)号：US5523542A
公开(公告)日：1996-06-04
申请号：US440751
申请日：1995-05-15
申请人： Anchor Chen , Gary Hong
发明人： Anchor Chen , Gary Hong
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , B23K9/00 , H01G7/00 , H01L21/70
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/92 , Y10T29/435
摘要： A random access memory (RAM) cell capacitor and its method of fabrication. A bottom electrode plate of the capacitor is provided with a plurality of islands disposed on the surface thereof so as to attain an increase in the capacitance thereof.
摘要翻译：随机存取存储器（RAM）单元电容器及其制造方法。电容器的底部电极板设置有设置在其表面上的多个岛以便获得其电容的增加。

16. 发明授权

US5472896A Method for fabricating polycide gate MOSFET devices 失效
标题翻译：制造多晶硅栅极MOSFET器件的方法
公开(公告)号：US5472896A
公开(公告)日：1995-12-05
申请号：US338951
申请日：1994-11-14
申请人： Anchor Chen , Gary Hong
发明人： Anchor Chen , Gary Hong
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/28061 , H01L29/6656
摘要： A method of fabricating MOSFET device with polycide gate, which includes a polysilicon layer and a refractory metal silicide layer, is described. After a thin oxide layer is formed by a thermal process, the refractory metal silicide layer is transformed from an amorphous form to a crystalline form that leads to peeling and surface roughness problems in the prior art. This method utilizes an additional ion implantation step to transform the refractory metal silicide layer from the crystalline form back into the amorphous form. Hence, the problems of peeling and surface roughness of the polycide gate can be overcome.
摘要翻译：描述了一种制造具有多晶硅栅极的MOSFET器件的方法，该器件包括多晶硅层和难熔金属硅化物层。在通过热处理形成薄氧化物层之后，难熔金属硅化物层从无定形形式转变成结晶形式，这导致现有技术中的剥离和表面粗糙度问题。该方法利用额外的离子注入步骤将难熔金属硅化物层从结晶形式转变成无定形形式。因此，可以克服多晶硅栅极的剥离和表面粗糙度问题。

17. 发明授权

US5429980A Method of forming a stacked capacitor using sidewall spacers and local oxidation 失效
标题翻译：使用侧壁间隔物和局部氧化形成堆叠电容器的方法
公开(公告)号：US5429980A
公开(公告)日：1995-07-04
申请号：US318423
申请日：1994-10-05
申请人： Ming-Tzong Yang , Anchor Chen , Chen-Chiu Hsue
发明人： Ming-Tzong Yang , Anchor Chen , Chen-Chiu Hsue
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/70 , H01L21/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/92 , Y10S438/947
摘要： A method for fabricating a capacitors on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a field effect transistor (FET), having one capacitor aligned over and contacting the source/drain of the FET in the device region. The capacitor is increased in capacitance by forming a double recess in the bottom electrodes of the storage capacitors. The method of forming the double recess utilizes a sidewall spacer and local oxidation technique. After forming the bottom electrode having the double recess an insulating layer having a high dielectric constant is deposited as the inter-electrode insulator and a stop electrode is formed, completing the storage capacitor and the dynamic random access memory (DRAM) storage cell.
摘要翻译：实现了在具有增加的电容的动态随机存取存储器（DRAM）单元上制造电容器的方法。电容器制造在具有有源器件区域的硅衬底上。器件区域包含场效应晶体管（FET），其具有在器件区域中对齐并接触FET的源极/漏极的一个电容器。通过在存储电容器的底部电极中形成双重凹槽，电容器增加电容。形成双凹槽的方法利用侧壁间隔件和局部氧化技术。在形成具有双凹槽的底部电极之后，沉积具有高介电常数的绝缘层作为电极间绝缘体并形成停止电极，从而完成存储电容器和动态随机存取存储器（DRAM）存储单元。

18. 发明授权

US07297991B2 Bipolar junction transistor and fabricating method 有权
标题翻译：双极结晶体管及其制造方法
公开(公告)号：US07297991B2
公开(公告)日：2007-11-20
申请号：US10709568
申请日：2004-05-14
申请人： Anchor Chen
发明人： Anchor Chen
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/11 , H01L27/082 , H01L27/102
CPC分类号： H01L29/66242 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/7378
摘要： A bipolar junction transistor includes a dielectric layer formed on a predetermined region of a substrate, an opening formed in the dielectric layer and a portion of the substrate being exposed, a semiconductor layer formed on a sidewall and a bottom of the opening and on a portion of the dielectric layer outside the opening, a spacer formed on the semiconductor layer to define a self-aligned emitter region in the opening, an emitter conductivity layer being filled with the self-aligned emitter region and a PN junction being formed between the emitter conductivity layer and the semiconductor layer, and a salicide layer formed on the emitter conductivity layer and on the portion of the semiconductor layer extending outside the opening.
摘要翻译：双极结晶体管包括形成在基板的预定区域上的电介质层，形成在电介质层中的开口和基板的一部分被露出的半导体层，形成在开口的侧壁和底部上的半导体层位于开口外部的电介质层，形成在半导体层上以形成开口中的自对准发射极区的间隔物，发射极传导层填充有自对准发射极区，并且PN结形成在发射极导电性之间层和半导体层，以及形成在发射极传导性层上的半导体层和在开口外部延伸的部分的自对准硅化物层。

19. 发明授权

US07211493B2 Variable capacitor structure and method of manufacture 有权
标题翻译：可变电容器结构及制造方法
公开(公告)号：US07211493B2
公开(公告)日：2007-05-01
申请号：US10630642
申请日：2003-07-29
申请人： Jin-Horng Gau , Anchor Chen
发明人： Jin-Horng Gau , Anchor Chen
IPC分类号： H01L21/20
CPC分类号： H01L27/0808
摘要： A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped well has a cavity. The first type ion-doped buried layer is in the substrate underneath the first type ion-doped well. The first type ion-doped buried layer and the first type ion-doped well are connected. The second type ion-doped region is at the bottom of the cavity of the first type ion-doped well. The conductive layer is above and in connection with the first type ion-doped buried layer.
摘要翻译：一种可变电容器，包括具有第一类型离子掺杂掩埋层，第一类型离子掺杂阱，第二类型离子掺杂区和其上的导电层的衬底。在衬底内形成第一种类型的离子掺杂阱。第一类离子掺杂阱具有空腔。第一类离子掺杂掩埋层位于第一类离子掺杂阱下的衬底中。连接第一种离子掺杂掩埋层和第一种离子掺杂阱。第二类离子掺杂区位于第一类型离子掺杂阱的空腔的底部。导电层位于第一类型的离子掺杂掩埋层之上并与之连接。

20. 发明授权

US06905935B1 Method for fabricating a vertical bipolar junction transistor 有权
标题翻译：用于制造垂直双极结型晶体管的方法
公开(公告)号：US06905935B1
公开(公告)日：2005-06-14
申请号：US10707260
申请日：2003-12-02
申请人： Jing-Horng Gau , Anchor Chen
发明人： Jing-Horng Gau , Anchor Chen
IPC分类号： H01L21/331 , H01L29/08 , H01L29/732
CPC分类号： H01L29/66272 , H01L29/0804 , H01L29/0821 , H01L29/7322
摘要： A semiconductor wafer includes a first doping region of a first conductivity type, a second doping region of a second conductivity type, and a plurality of isolated structures positioned on surfaces of the first doping region and the second doping region. A third doping region of the first conductivity type is formed in an upper portion of the second doping region. A shielding layer is formed and a portion of the shielding layer is removed to form an opening shielding layer to expose a portion of the third doping region. Subsequently, a doping layer of the second conductivity type is formed on a surface of the third doping region. A self-aligned silicidation process is performed to form a silicide layer on the surfaces of the second doping region, the third doping region and the doping layer, the silicide layer functioning as a contact region of a vertical bipolar junction transistor.
摘要翻译：半导体晶片包括第一导电类型的第一掺杂区域，第二导电类型的第二掺杂区域和位于第一掺杂区域和第二掺杂区域的表面上的多个隔离结构。第一导电类型的第三掺杂区形成在第二掺杂区的上部。形成屏蔽层，并且去除屏蔽层的一部分以形成露出第三掺杂区域的一部分的开口屏蔽层。随后，在第三掺杂区的表面上形成第二导电类型的掺杂层。执行自对准硅化工艺以在第二掺杂区域，第三掺杂区域和掺杂层的表面上形成硅化物层，硅化物层用作垂直双极结型晶体管的接触区域。

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