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11. 发明授权

US06987042B2 Method of forming a collar using selective SiGe/Amorphous Si Etch 失效
标题翻译：使用选择性SiGe /无定形Si蚀刻法形成套环的方法
公开(公告)号：US06987042B2
公开(公告)日：2006-01-17
申请号：US10250046
申请日：2003-05-30
申请人： Jochen Beintner , Naim Moumen , Porshia S. Wrschka
发明人： Jochen Beintner , Naim Moumen , Porshia S. Wrschka
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L21/30604 , H01L29/66181 , H01L29/945
摘要： A method of forming collar isolation for a trench storage memory cell structure is provided in which amorphous Si (a:Si) and silicon germanium (SiGe) are first formed into a trench structure. An etching process that is selective to a:Si as compared to SiGe is employed in defining the regions in which the collar isolation will be formed. The selective etching process employed in the present invention is a wet etch process that includes etching with HF, rinsing, etching with NH4OH, rinsing, and drying with a monohydric alcohol such as isopropanol. The sequence of NH4OH etching and rinsing may be repeated any number of times. The conditions used in the selective etching process of the present invention are capable of etching a:Si at a faster rate than SiGe.
摘要翻译：提供了一种形成沟槽存储单元结构的套环隔离的方法，其中首先将非晶硅（a：Si）和硅锗（SiGe）形成沟槽结构。与SiGe相比，对a：Si有选择性的蚀刻工艺用于限定将形成套环隔离的区域。在本发明中采用的选择性蚀刻方法是湿式蚀刻工艺，其包括用HF蚀刻，漂洗，用NH 4 OH蚀刻，漂洗和用一元醇如异丙醇干燥。 NH 4 OH蚀刻和漂洗的顺序可以重复任意次数。在本发明的选择性蚀刻工艺中使用的条件能够以比SiGe更快的速度蚀刻Si。

12. 发明申请

US20050158927A1 Structure and method of forming a notched gate field effect transistor 有权
公开(公告)号：US20050158927A1
公开(公告)日：2005-07-21
申请号：US11059819
申请日：2005-02-17
申请人： Jochen Beintner , Yujun Li , Naim Moumen , Porshia Wrschka
发明人： Jochen Beintner , Yujun Li , Naim Moumen , Porshia Wrschka
IPC分类号： H01L29/423 , H01L21/265 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L29/786 , H01L21/00 , H01L21/8238 , H01L21/84
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/28044 , H01L21/28114 , H01L29/42376 , H01L29/49 , H01L29/665 , Y10S438/933
摘要： The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.

13. 发明授权

US06579768B2 Field effect transistor and method of fabrication 有权
公开(公告)号：US06579768B2
公开(公告)日：2003-06-17
申请号：US10066184
申请日：2002-01-31
申请人： Peter Thwaite , Jochen Beintner
发明人： Peter Thwaite , Jochen Beintner
IPC分类号： H01L21336
CPC分类号： H01L29/1033 , H01L21/76235
摘要： An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge of the channel region. A method of controlling the shape of the edge of the channel region is to limit the supply of oxygen to the region at the edge of the channel region during the oxidation process when the side walls of the silicon island, in which the transistor will be formed, are initially covered with a layer of silicon oxide.

14. 发明授权

US08963294B2 Dense chevron finFET and method of manufacturing same 有权
标题翻译：密集人字形finFET及其制造方法
公开(公告)号：US08963294B2
公开(公告)日：2015-02-24
申请号：US11857806
申请日：2007-09-19
申请人： Jochen Beintner , Thomas Ludwig , Edward Joseph Nowak
发明人： Jochen Beintner , Thomas Ludwig , Edward Joseph Nowak
IPC分类号： H01L29/04 , H01L21/84 , H01L27/12 , H01L29/66 , H01L29/78
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.
摘要翻译：用于形成finFET的方法，结构和取向程序。该方法包括：用第一掩模限定finFET的第一鳍片，并用第二掩模限定finFET的第二鳍片。该结构包括单晶半导体材料的整体第一和第二鳍片以及第一和第二鳍片的纵向轴线在相同的晶体方向上排列但彼此偏移。对准过程包括同时将栅极掩模上的对准标记对准由通过用于限定第一鳍片的第一掩模单独形成的对准靶和用于限定第二鳍片的第二掩模。

15. 发明授权

US07737502B2 Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI sructure with elevated source/drain 有权
标题翻译：用于提高源/漏极的应变Si / SGOI结构上的多栅极氧化和侧壁保护的提高的STI工艺
公开(公告)号：US07737502B2
公开(公告)日：2010-06-15
申请号：US11351801
申请日：2006-02-10
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
IPC分类号： H01L27/088
CPC分类号： H01L29/66628 , H01L21/76243 , H01L21/76251 , H01L29/1054 , H01L29/41783 , H01L29/516 , H01L29/517 , H01L29/6653 , H01L29/66742 , H01L29/7842 , H01L29/78687 , Y10S438/938
摘要： The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.
摘要翻译：本发明提供了一种应变/ SGOI结构，其包括弛豫SiGe层的有源器件区，位于松弛SiGe层顶部的应变Si层，位于应变Si层的一部分顶部的凸起的源/漏区，以及包括位于应变Si层的另一部分上的至少栅极电介质和栅极多晶硅的堆叠; 以及围绕有源器件区域的凸起的沟槽氧化物区域。本发明还提供了一种形成这种结构的方法。在本发明的方法中，在沟槽隔离形成之前形成栅极电介质，从而避免了与在栅极电介质形成之前形成沟槽氧化物的现有技术工艺相关的许多问题。

16. 发明授权

US07696539B2 Device fabrication by anisotropic wet etch 失效
标题翻译：通过各向异性湿法蚀刻的器件制造
公开(公告)号：US07696539B2
公开(公告)日：2010-04-13
申请号：US12141878
申请日：2008-06-18
申请人： Yujun Li , Kenneth T. Settlemyer, Jr. , Jochen Beintner
发明人： Yujun Li , Kenneth T. Settlemyer, Jr. , Jochen Beintner
IPC分类号： H01L29/80
CPC分类号： H01L21/84 , H01L21/30608 , H01L27/1203 , H01L29/045 , H01L29/66772 , H01L29/66818 , H01L29/785
摘要： A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.
摘要翻译：提出了一种制造方法和场效应器件结构，其减少源/漏电容并允许器件接触。产生基于Si的材料基座，其顶表面和其侧壁的方向定位成与基座和支撑构件的选定结晶平面基本平行。用包含氢氧化铵的各向异性溶液湿式蚀刻基座。基座的侧壁变小，在基座上形成截面减小的部分。选择减小的横截面段中的掺杂剂浓度足够高以使其提供穿过基座的电连续性。

17. 发明授权

US07470570B2 Process for fabrication of FinFETs 有权
标题翻译： FinFET的制造工艺
公开(公告)号：US07470570B2
公开(公告)日：2008-12-30
申请号：US11559460
申请日：2006-11-14
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L21/00
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

18. 发明申请

US20080111184A1 PROCESS FOR FABRICATION OF FINFETs 有权
标题翻译： FINFET制造工艺
公开(公告)号：US20080111184A1
公开(公告)日：2008-05-15
申请号：US11559460
申请日：2006-11-14
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

19. 发明授权

US06998666B2 Nitrided STI liner oxide for reduced corner device impact on vertical device performance 有权
标题翻译：氮化氮化物衬垫氧化物，用于减少拐角装置对垂直装置性能的影响
公开(公告)号：US06998666B2
公开(公告)日：2006-02-14
申请号：US10707754
申请日：2004-01-09
申请人： Jochen Beintner , Rama Divakaruni , Rajarao Jammy
发明人： Jochen Beintner , Rama Divakaruni , Rajarao Jammy
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10894
摘要： A method of fabricating an integrated circuit device comprises etching a trench in a substrate and forming a dynamic random access memory (DRAM) cell having a storage capacitor at a lower end and an overlying vertical metal oxide semiconductor field effect transistor (MOSFET) comprising a gate conductor and a boron-doped channel. The method includes forming trenches adjacent the DRAM cell and a silicon-oxy-nitride isolation liner on either side of the DRAM cell, adjacent the gate conductor. Isolation regions are then formed in the trenches on either side of the DRAM cell. Thereafter, the DRAM cell, including the boron-containing channel region adjacent the gate conductor, is subjected to elevated temperatures by thermal processing, for example, forming a support device on the substrate adjacent the isolation regions. The nitride-containing isolation liner reduces segregation of the boron in the channel region, as compared to an essentially nitrogen-free oxide-containing isolation liner.
摘要翻译：一种制造集成电路器件的方法包括蚀刻衬底中的沟槽并形成具有位于下端的存储电容器的动态随机存取存储器（DRAM）单元和覆盖的垂直金属氧化物半导体场效应晶体管（MOSFET），其包括栅极导体和掺硼通道。该方法包括在DRAM单元附近形成沟槽和在DRAM单元的任一侧上与栅极导体相邻的硅 - 氮氧化物隔离衬垫。然后在DRAM单元的两侧的沟槽中形成隔离区。此后，包括与栅极导体相邻的含硼沟道区域的DRAM单元通过热处理受到升高的温度，例如，在邻近隔离区域的衬底上形成支撑器件。与基本上不含氮氧化物的隔离衬垫相比，含氮化物的隔离衬垫减少了沟道区域中的硼的偏析。

20. 发明授权

US06946345B2 Self-aligned buried strap process using doped HDP oxide 失效
标题翻译：使用掺杂HDP氧化物的自对准掩埋工艺
公开(公告)号：US06946345B2
公开(公告)日：2005-09-20
申请号：US10688612
申请日：2003-10-17
申请人： Jochen Beintner , Wolfgang Bergner , Richard A. Conti , Andreas Knorr , Rolf Weis
发明人： Jochen Beintner , Wolfgang Bergner , Richard A. Conti , Andreas Knorr , Rolf Weis
IPC分类号： H01L21/8242 , H01L29/94 , H01L21/20
CPC分类号： H01L27/10867 , H01L27/10864 , H01L29/945
摘要： The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.
摘要翻译：本发明提供了一种沟槽存储结构，其包括具有沟槽的衬底，沟槽下部的电容器导体，与电容器导体相邻的沟槽中的导电节点带，电容器导体上方的沟槽顶部氧化物，以及导电埋在衬底中的邻近沟槽顶部氧化物的衬底。沟槽顶部氧化物包括导电带上方的掺杂沟槽顶部氧化物层和掺杂沟槽顶部氧化物层上方的未掺杂沟槽顶部氧化物层。

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