专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08928346B2 Method for an improved checking of repeatability and reproducibility of a measuring chain for semiconductor device testing 有权
标题翻译：用于半导体器件测试的测量链的重复性和再现性的改进的检查方法
公开(公告)号：US08928346B2
公开(公告)日：2015-01-06
申请号：US13092772
申请日：2011-04-22
申请人： Sergio Tenucci , Alberto Pagani , Marco Spinetta , Bernard Ranchoux
发明人： Sergio Tenucci , Alberto Pagani , Marco Spinetta , Bernard Ranchoux
IPC分类号： G01R31/26 , G05B19/418 , G01R31/28
CPC分类号： G05B19/41875 , G01R31/2894 , Y02P90/22 , Y02P90/86
摘要： A method provides an improved checking of repeatability and reproducibility of a measuring chain, in particular for quality control by semiconductor device testing. The method includes testing steps provided for multiple and different devices to be subjected to measurement or control through a measuring system that includes at least one chain of measuring units between a testing apparatus (ATE) and each device to be subjected to measurement or control. Advantageously, the method comprises checking repeatability and reproducibility of each type of unit that forms part of the measuring chain and, after the checking, making a correlation between the various measuring chains as a whole to check repeatability and reproducibility, using a corresponding device subjected to measurement or control.
摘要翻译：一种方法提供了对测量链的重复性和再现性的改进的检查，特别是通过半导体器件测试的质量控制。该方法包括对通过测量系统进行测量或控制的多个和不同设备提供的测试步骤，所述测量系统包括测试装置（ATE）和要进行测量或控制的每个设备之间的至少一个测量单元链。有利地，该方法包括检查构成测量链的一部分的每种类型的单元的重复性和再现性，并且在检查之后，使各种测量链之间的相关性作为整体来检查重复性和再现性，使用受到测量或控制。

12. 发明授权

US08907693B2 Electromagnetic shield for testing integrated circuits 有权
标题翻译：用于测试集成电路的电磁屏蔽
公开(公告)号：US08907693B2
公开(公告)日：2014-12-09
申请号：US12851680
申请日：2010-08-06
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： G01R31/28 , G01R1/18 , G01R1/067 , G01R1/073
CPC分类号： G01R1/18 , G01R1/06772 , G01R1/07307 , G01R31/2884 , G01R31/2886
摘要： An embodiment of a probe card is proposed. The probe card comprises a plurality of probes. Each probe is adapted to contact a corresponding terminal of a circuit integrated in at least one die of a semiconductor material wafer during a test phase of the wafer. Said plurality of probes includes at least one probe adapted to provide and/or receive a radio frequency test signal to/from the corresponding terminal during the test phase. Said probe card comprises at least one electromagnetic shield structure corresponding to the at least one probe adapted to provide and/or receive the radio frequency test signal for the at least partial shielding of an electromagnetic field irradiated by such at least one probe adapted to provide and/or receive the radio frequency test signal.
摘要翻译：提出了一种探针卡的实施例。探针卡包括多个探针。每个探针适于在晶片的测试阶段期间接触集成在半导体材料晶片的至少一个管芯中的电路的相应端子。所述多个探头包括适于在测试阶段期间向/从相应终端提供和/或接收射频测试信号的至少一个探头。所述探针卡包括对应于所述至少一个探头的至少一个电磁屏蔽结构，所述至少一个探针适于提供和/或接收射频测试信号，用于对由至少一个探头照射的电磁场的至少部分屏蔽， /或接收射频测试信号。

13. 发明申请

US20110186838A1 CIRCUIT ARCHITECTURE FOR THE PARALLEL SUPPLYING DURING AN ELECTRIC OR ELECTROMAGNETIC TESTING OF A PLURALITY OF ELECTRONIC DEVICES INTEGRATED ON A SEMICONDUCTOR WAFER 有权
标题翻译：用于在半导体波形集成的大量电子器件进行电气或电磁测试期间并联供电的电路架构
公开(公告)号：US20110186838A1
公开(公告)日：2011-08-04
申请号：US13022419
申请日：2011-02-07
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： H01L23/48 , H01L21/66
CPC分类号： H01L22/32 , G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： A circuit architecture provides for the parallel supplying of power during electric or electromagnetic testing of electronic devices integrated on a same semiconductor wafer and bounded by scribe lines. The circuit architecture comprises a conductive grid interconnecting the electronic devices and having a portion external to the devices and a portion internal to the devices. The external portion extends along the scribe lines; and the internal portion extends within at least a part of the devices. The circuit architecture includes interconnection pads between the external portion and the internal portion of the conductive grid and provided on at least a part of the devices, the interconnection pads forming, along with the internal and external portions, power supply lines which are common to different electronic devices of the group.
摘要翻译：电路架构提供了在同一半导体晶片上并且由划线界定的电子设备的电或电磁测试期间并联供电。电路架构包括将电子设备互连并且具有设备外部的部分和设备内部的部分的导电栅格。外部部分沿划线延伸; 并且内部部分在装置的至少一部分内延伸。电路结构包括在导电栅格的外部部分和内部部分之间并且设置在至少一部分器件上的互连焊盘，互连焊盘与内部和外部部分形成不同的电源线电子设备组。

14. 发明申请

US20100134133A1 METHOD FOR PERFORMING AN ELECTRICAL TESTING OF ELECTRONIC DEVICES 有权
标题翻译：用于执行电子设备电气测试的方法
公开(公告)号：US20100134133A1
公开(公告)日：2010-06-03
申请号：US12625188
申请日：2009-11-24
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： G01R31/02
CPC分类号： G01R31/31713
摘要： A method of electrical testing electronic devices DUT, comprising: connecting at least an electronic device DUT to an automatic testing apparatus suitable for performing the testing of digital circuits or memories or of digital circuits and memories; sending electrical testing command signals to the electronic device DUT by means of the ATE apparatus; performing electrical testing of the electronic device DUT by means of at least one advanced supervised self testing system “Advanced Low Pin Count BIST” ALB which is built in the electronic device DUT, the ALB system being digitally interfaced with the ATE through a dedicated digital communication channel; and sending reply messages, if any, which comprise measures, failure information and reply data to the command signals from the electronic device DUT toward the ATE apparatus by means of the digital communication channel.
摘要翻译：一种电气测试电子设备DUT的方法，包括：至少将电子设备DUT连接到适于执行数字电路或存储器或数字电路和存储器的测试的自动测试设备; 通过ATE设备向电子设备DUT发送电测试命令信号; 通过至少一个高级监督自检系统“内置在电子设备DUT”中的“高级低引脚数BIST”ALB进行电子设备DUT的电气测试，ALB系统通过专用数字通信与ATE进行数字接口渠道; 并且通过数字通信信道向电子设备DUT向ATE设备发送包括测量，故障信息和答复数据的回复消息（如果有的话）到命令信号。

15. 发明授权

US09275962B2 Probe pad with indentation 有权
标题翻译：带缩进的探针垫
公开(公告)号：US09275962B2
公开(公告)日：2016-03-01
申请号：US13106557
申请日：2011-05-12
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： H01L23/00
CPC分类号： H01L22/32 , G01R31/2886 , H01L21/76877 , H01L23/528 , H01L23/53209 , H01L23/53242 , H01L23/53257 , H01L24/05 , H01L24/92 , H01L2224/04042 , H01L2224/05082 , H01L2224/05144 , H01L2224/05155 , H01L2224/05157 , H01L2224/05164 , H01L2224/05173 , H01L2224/05557 , H01L2224/05644 , H01L2224/05664 , H01L2224/48463 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01046 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/19041 , H01L2924/00014 , H01L2924/00
摘要： An integrated electronic circuit having probe indentations filled by a hard covering substance. The integrated circuit device results from a process of manufacture including forming a substrate comprising a plurality of functional components of the electronic circuit, creating a plurality of conductive layers on such substrate to form an electric contact region with high hardness equal to or greater than a first hardness value of about 300 HV, contacting the electric contact region with a probe thereby causing an indentation. In an embodiment, the process further comprises, after the test run, creating a covering conductive layer on at least one part of the electric contact region contacted by the probe to fill the indentation.
摘要翻译：具有由硬覆盖物质填充的探针压痕的集成电子电路。集成电路装置来自制造工艺，包括形成包括电子电路的多个功能部件的基板，在该基板上形成多个导电层，以形成等于或大于第一硬度值约为300HV，使电接触区域与探针接触，从而形成压痕。在一个实施例中，该方法还包括在测试运行之后，在由探针接触的电接触区域的至少一部分上形成覆盖导电层以填充凹陷。

16. 发明授权

US09146273B2 Process for controlling the correct positioning of test probes on terminations of electronic devices integrated on a semiconductor and corresponding electronic device 有权
标题翻译：用于控制测试探针在集成在半导体和相应的电子设备上的电子设备的终端上的正确定位的过程
公开(公告)号：US09146273B2
公开(公告)日：2015-09-29
申请号：US12974957
申请日：2010-12-21
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： G01R31/00 , G01R31/28
CPC分类号： G01R31/2884 , G01R31/2889 , G01R31/2891
摘要： An embodiment for making a check of the electric type executed on wafer for testing the correct positioning or alignment of the probes of a probe card on the pads or bumps of the electronic devices integrated on semiconductor wafer. An embodiment consists in making a current circulate in at least part of the seal ring of at least one of the above devices, and in case it has to flow in the seal ring of more devices, these seal rings are suitably interconnected to each other. Thanks to an embodiment the seal ring may also be reinforced in the angle areas of the chip, and suitable circuits may be possibly inserted in the seal ring or between the seal rings.
摘要翻译：用于检查在晶片上执行的电气类型的实施例，用于测试探针卡的探针在集成在半导体晶片上的电子器件的焊盘或凸块上的正确定位或对准。一个实施例在于使电流在上述装置中的至少一个的密封环的至少一部分中循环，并且在其必须在更多装置的密封环中流动的情况下，这些密封环适当地彼此互连。由于实施例，密封环也可以在芯片的角度区域中被加强，并且合适的电路可能可能插入密封环中或密封环之间。

17. 发明授权

US09000788B2 Method for performing an electrical testing of electronic devices 有权
标题翻译：执行电子设备电气测试的方法
公开(公告)号：US09000788B2
公开(公告)日：2015-04-07
申请号：US12625188
申请日：2009-11-24
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： G01R31/3187 , G01R31/317
CPC分类号： G01R31/31713
摘要： A method of electrical testing electronic devices DUT, comprising: connecting at least an electronic device DUT to an automatic testing apparatus suitable for performing the testing of digital circuits or memories or of digital circuits and memories; sending electrical testing command signals to the electronic device DUT by means of the ATE apparatus; performing electrical testing of the electronic device DUT by means of at least one advanced supervised self testing system “Advanced Low Pin Count BIST” ALB which is built in the electronic device DUT, the ALB system being digitally interfaced with the ATE through a dedicated digital communication channel; and sending reply messages, if any, which comprise measures, failure information and reply data to the command signals from the electronic device DUT toward the ATE apparatus by means of the digital communication channel.
摘要翻译：一种电气测试电子设备DUT的方法，包括：至少将电子设备DUT连接到适于执行数字电路或存储器或数字电路和存储器的测试的自动测试设备; 通过ATE设备向电子设备DUT发送电测试命令信号; 通过至少一个高级监督自检系统“内置在电子设备DUT”中的“高级低引脚数BIST”ALB进行电子设备DUT的电气测试，ALB系统通过专用数字通信与ATE进行数字接口渠道; 并且通过数字通信信道向电子设备DUT向ATE设备发送包括测量，故障信息和答复数据的回复消息（如果有的话）到命令信号。

18. 发明授权

US08829931B2 Testing method for semiconductor integrated electronic devices and corresponding test architecture 有权
标题翻译：半导体集成电子设备的测试方法及相应的测试架构
公开(公告)号：US08829931B2
公开(公告)日：2014-09-09
申请号：US13252895
申请日：2011-10-04
申请人： Alberto Pagani , Jean-Michel Bard
发明人： Alberto Pagani , Jean-Michel Bard
IPC分类号： G01R31/00 , G06F11/26
CPC分类号： G06F11/26
摘要： A testing method is described of at least one device provided with an integrated testing circuit and in communication with at least one tester where messages/instructions/test signals/information are exclusively sent from the tester to the device. A testing architecture is also described for implementing this testing method.
摘要翻译：描述了至少一个设置有集成测试电路并且与至少一个测试器进行通信的测试方法，其中消息/指令/测试信号/信息从测试仪专门发送到设备。还描述了用于实现该测试方法的测试架构。

19. 发明授权

US08643395B2 Crosstalk suppression in wireless testing of semiconductor devices 有权
标题翻译：半导体器件无线测试中的串扰抑制
公开(公告)号：US08643395B2
公开(公告)日：2014-02-04
申请号：US13006942
申请日：2011-01-14
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： G01R31/02
CPC分类号： G01R31/2851 , G01R31/2886 , G01R31/3025 , G01R31/303 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die.
摘要翻译：一种集成在半导体材料裸片上并适于至少部分地被无线测试的集成电路，其中用于设置用于集成电路的无线测试的所选无线电通信频率的电路集成在半导体材料裸片上。

20. 发明授权

US08441272B2 MEMS probe for probe cards for integrated circuits 有权
标题翻译：用于集成电路的探针卡的MEMS探针
公开(公告)号：US08441272B2
公开(公告)日：2013-05-14
申请号：US12649109
申请日：2009-12-29
申请人： Alberto Pagani
发明人： Alberto Pagani
IPC分类号： G01R1/067
CPC分类号： G01R1/06716 , G01R1/06727 , G01R1/06733
摘要： A MEMS probe adapted to contact a corresponding terminal of an integrated circuit, integrated on at least one chip of a semiconductor material wafer during a test phase of the wafer is provided. The probe includes a support structure comprising a first access terminal and a second access terminal; the support structure defines a conductive path between said first access terminal and said second access terminal. The probes further-includes a probe region connected to the support structure adapted to contact the corresponding terminal of the integrated circuit during the test phase for providing at least one test signal received from the first access terminal and the second access terminal to the integrated circuit through at least one portion of the conductive path, and/or providing at least one test signal generated by the integrated circuit to at least one between the first access terminal and the second access terminal trough at least one portion of the conductive path. The probe region is arranged on the conductive path of the support structure between said first access terminal and said second access terminal.
摘要翻译：提供一种MEMS探针，其适于在晶片的测试阶段期间与集成在半导体材料晶片的至少一个芯片上的集成电路的相应端子接触。探针包括支撑结构，该支撑结构包括第一接入终端和第二接入终端; 所述支撑结构限定所述第一接入终端与所述第二接入终端之间的导电路径。所述探头进一步包括连接到所述支撑结构的探针区域，所述探测区域在所述测试阶段期间与所述集成电路的相应端子接触，以便从所述第一接入终端接收的至少一个测试信号和所述第二接入终端通过所述导电路径的至少一部分，和/或将由所述集成电路产生的至少一个测试信号提供给所述第一接入终端和所述第二接入终端之间的至少一个在所述导电路径的至少一部分。探针区域布置在所述第一接入终端和所述第二接入终端之间的支撑结构的导电路径上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式