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11. 发明授权

US5840200A Method of manufacturing semiconductor devices 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5840200A
公开(公告)日：1998-11-24
申请号：US788310
申请日：1997-01-24
申请人： Satoshi Nakagawa , Toyoji Ito , Yoji Bito , Yoshihisa Nagano
发明人： Satoshi Nakagawa , Toyoji Ito , Yoji Bito , Yoshihisa Nagano
IPC分类号： H01L21/02 , H01L21/311 , H01L21/3213 , H01L21/302
CPC分类号： H01L28/55 , H01L21/31122 , H01L21/32136
摘要： A device insulating film, a lower-layer platinum film, a ferroelectric film, an upper-layer platinum film, and a titanium film are sequentially formed on a semiconductor substrate in this order. On the titanium film, a photoresist mask is further formed in a desired pattern. The thickness of the titanium film is adjusted to be 1/10 or more of the total thickness of a multilayer film consisting of the upper-layer platinum film, the ferroelectric film, and the lower-layer platinum film. The titanium film is then subjected to dry etching and the photoresist film is removed by ashing process. The titanium film thus patterned is used as a mask in etching the upper-layer platinum film, the ferroelectric film, and the lower-layer platinum film by a dry-etching method using a plasma of a gas mixture of chlorine and oxygen in which the volume concentration of oxygen gas is adjusted to be 40%. During the dry-etching process, the titanium film is oxidized to provide a high etching selectivity. Subsequently, the titanium film is removed by dry etching using a plasma of chlorine gas.
摘要翻译：依次在半导体衬底上依次形成器件绝缘膜，下层铂膜，铁电体膜，上层铂膜和钛膜。在钛膜上，以期望的图案进一步形成光致抗蚀剂掩模。将钛膜的厚度调节为由上层铂膜，铁电体膜和下层铂膜构成的多层膜的总厚度的+ E，fra 1/10 + EE以上。然后对钛膜进行干蚀刻，并通过灰化处理去除光致抗蚀剂膜。通过使用氯气和氧气的混合气体的等离子体的干蚀刻方法，将如此构图的钛膜用作蚀刻上层铂膜，铁电体膜和下层铂膜的掩模，其中氧气体积浓度调整为40％。在干蚀刻工艺期间，钛膜被氧化以提供高蚀刻选择性。随后，使用氯气等离子体通过干蚀刻除去钛膜。

12. 发明授权

US5780351A Semiconductor device having capacitor and manufacturing method thereof 失效
标题翻译：具有电容器的半导体器件及其制造方法
公开(公告)号：US5780351A
公开(公告)日：1998-07-14
申请号：US844108
申请日：1997-04-28
申请人： Koji Arita , Eiji Fujii , Yasuhiro Shimada , Yasuhiro Uemoto , Toru Nasu , Akihiro Matsuda , Yoshihisa Nagano , Atsuo Inoue , Taketoshi Matsuura , Tatsuo Otsuki
发明人： Koji Arita , Eiji Fujii , Yasuhiro Shimada , Yasuhiro Uemoto , Toru Nasu , Akihiro Matsuda , Yoshihisa Nagano , Atsuo Inoue , Taketoshi Matsuura , Tatsuo Otsuki
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/115 , H01L21/20 , H01L21/00
CPC分类号： H01L27/11502 , H01L27/10852 , H01L27/11585 , H01L27/1159 , H01L28/40 , H01L28/55 , H01L28/60 , H01L28/75 , Y10S438/958
摘要： A semi conductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
摘要翻译：一种半导体器件，其在形成集成电路的半导体衬底上通过层间绝缘层形成电容器。该半导体装置具有含水量为0.5g / cm 3以下的层间绝缘层，其在一个方面覆盖电容器，并且具有氢含量为1021原子/ cm3以下的钝化层，其覆盖电容器的互连在其他方面。通过这样构成，可以防止导致铁电层或高介电层的电可靠性的电容器电介质的劣化。

13. 发明授权

US5599424A Method of manufacturing semiconductor devices 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5599424A
公开(公告)日：1997-02-04
申请号：US571732
申请日：1995-12-13
申请人： Shoji Matsumoto , Yoshihisa Nagano , Yasuhiro Shimada , Yasufumi Izutsu
发明人： Shoji Matsumoto , Yoshihisa Nagano , Yasuhiro Shimada , Yasufumi Izutsu
IPC分类号： H01L21/302 , H01L21/02 , H01L21/3065 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108 , H01L21/00
CPC分类号： H01L28/40
摘要： On a silicon substrate, a silicon oxide layer, a first platinum layer, a dielectric film and a second platinum layer are formed, and then the second platinum layer and the dielectric film are dry etched, via a resist layer, in a 1-5 Pa low pressure region with a mixed gas of HBr and 0.sub.2 as the etching gas. As soon as the first platinum layer is exposed, the unetched portion of dielectric film is etched off in a 5-50 Pa high pressure region, and then the first platinum layer is dry etched again in the low pressure region to form a capacitor consisting of a top electrode, a capacitance insulation layer and a bottom electrode in a semiconductor integrated circuit chip. Using this manufacturing method prevents the deterioration in definition caused by the use of a thick resist and the operation failure of circuit elements such as transistors due to over etching on the insulation layer.
摘要翻译：在硅衬底上形成氧化硅层，第一铂层，电介质膜和第二铂层，然后通过抗蚀剂层在1-5中干法蚀刻第二铂层和电介质膜 Pa低压区域，混合气体为HBr和O2作为蚀刻气体。一旦露出第一铂层，在5-50Pa高压区域中蚀刻介电膜的未蚀刻部分，然后在低压区域再次干法蚀刻第一铂层，形成由半导体集成电路芯片中的顶部电极，电容绝缘层和底部电极。使用该制造方法可以防止由于在绝缘层上的过度蚀刻而使用厚的抗蚀剂引起的定义的劣化以及诸如晶体管的电路元件的操作故障。

14. 发明授权

US08954182B2 Robot system 有权
标题翻译：机器人系统
公开(公告)号：US08954182B2
公开(公告)日：2015-02-10
申请号：US13221013
申请日：2011-08-30
申请人： Takeshi Okamoto , Kenji Matsufuji , Takurou Yano , Takuya Murayama , Yoshihisa Nagano
发明人： Takeshi Okamoto , Kenji Matsufuji , Takurou Yano , Takuya Murayama , Yoshihisa Nagano
IPC分类号： G06F19/00 , B25J9/16
CPC分类号： B25J9/1697 , B25J9/1682 , G05B2219/39109 , G05B2219/40053 , Y10S901/30
摘要： A robot system includes a manipulator; a work table arranged within a movement extent of the manipulator; an imaging unit for taking a two-dimensional image of the workpieces loaded on the work table; a workpiece supply unit for supplying workpieces onto the work table; and a control system for controlling operations of the manipulator and the imaging unit. The control system includes an imaging control unit for controlling the imaging unit to take the two-dimensional image of the workpieces loaded on the work table, a workpiece detecting unit for detecting a position and a posture of each of the workpieces loaded on the work table by comparing the two-dimensional image taken by the imaging unit with templates stored in advance, and a manipulator control unit for operating the manipulator to perform a work with respect to the workpieces detected by the workpiece detecting unit.
摘要翻译：机器人系统包括操纵器; 布置在机械手的移动范围内的工作台; 用于拍摄加载在工作台上的工件的二维图像的成像单元; 工件供给单元，用于将工件供给到工作台上; 以及用于控制操纵器和成像单元的操作的控制系统。该控制系统包括：成像控制单元，用于控制成像单元以取得装载在工作台上的工件的二维图像;工件检测单元，用于检测装载在工作台上的每个工件的位置和姿势通过将成像单元拍摄的二维图像与预先存储的模板进行比较，以及操作器控制单元，用于操作操纵器以对由工件检测单元检测到的工件进行工作。

15. 发明授权

US07221013B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07221013B2
公开(公告)日：2007-05-22
申请号：US10916645
申请日：2004-08-12
申请人： Satoru Goto , Yoshihisa Nagano
发明人： Satoru Goto , Yoshihisa Nagano
IPC分类号： H01L27/108 , H01L29/76 , H01L31/119 , H01L21/00
CPC分类号： H01L28/55 , H01L27/10852 , H01L28/65 , H01L28/82
摘要： A semiconductor device includes: an insulating underlying layer of which surface portion has a concave portion; a lower electrode formed on the underlying layer along the inner face of the concave portion; a capacitor insulating film formed on the lower electrode and made of a high-dielectric or a ferroelectric subjected to thermal treatment for crystallization; and an upper electrode formed on the capacitor insulating film. The lower electrode and the upper electrode are made of a material that generates tensile stress in the thermal treatment for the capacitor insulating film, and the upper end part of the side wall and the corner part at the bottom face of the concave portion of the underlying layer are rounded.
摘要翻译：半导体器件包括：表面部分具有凹部的绝缘下层; 沿着所述凹部的内表面形成在所述下层上的下电极; 在下电极上形成的电容器绝缘膜，由用于结晶的热处理的高电介质或铁电体构成; 以及形成在电容器绝缘膜上的上电极。下电极和上电极由在电容绝缘膜的热处理中产生拉伸应力的材料制成，并且侧壁的上端部和位于底部的凹部的底部的底面的角部层是圆形的。

16. 发明申请

US20050006684A1 Capacitive element and semiconductor memory device 失效
标题翻译：电容元件和半导体存储器件
公开(公告)号：US20050006684A1
公开(公告)日：2005-01-13
申请号：US10916482
申请日：2004-08-12
申请人： Yoshihisa Nagano , Shinichiro Hayashi
发明人： Yoshihisa Nagano , Shinichiro Hayashi
IPC分类号： H01L21/02 , H01L21/8242 , H01L29/76
CPC分类号： H01L28/55 , H01L27/10852 , H01L28/65 , H01L28/90
摘要： A capacitive element includes a lower electrode having a three-dimensional shape, an upper electrode formed so as to be opposed to the lower electrode, and a capacitor insulating film formed between the lower and upper electrodes and made of a crystallized ferroelectric material. The thickness of the capacitor insulating film is set at 12.5 through 100 nm both inclusive.
摘要翻译：电容元件包括具有三维形状的下电极，形成为与下电极相对的上电极，以及形成在下电极和上电极之间并由结晶铁电材料制成的电容器绝缘膜。电容绝缘膜的厚度设定为12.5〜100nm。

17. 发明授权

US06468875B2 Fabrication method of capacitor for integrated circuit 失效
标题翻译：集成电路电容器的制作方法
公开(公告)号：US06468875B2
公开(公告)日：2002-10-22
申请号：US09768170
申请日：2001-01-24
申请人： Yasuhiro Uemoto , Eiji Fujii , Koji Arita , Yoshihisa Nagano , Yasuhiro Shimada , Masamichi Azuma , Atsuo Inoue , Yasufumi Izutsu
发明人： Yasuhiro Uemoto , Eiji Fujii , Koji Arita , Yoshihisa Nagano , Yasuhiro Shimada , Masamichi Azuma , Atsuo Inoue , Yasufumi Izutsu
IPC分类号： H01L2120
CPC分类号： H01L27/11502 , H01L28/40 , H01L28/56
摘要： A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.
摘要翻译：一种用于制造用于集成电路的电容器的方法，包括以下步骤：在衬底上形成用于粘附层的钛膜，通过在离子注入氧离子之后将钛膜退火形成用于扩散阻挡层的二氧化钛膜钛膜的表面区域，以将表面区域中的钛变为二氧化钛，并在二氧化钛膜上形成高介电常数电容器。

18. 发明授权

US06448598B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06448598B2
公开(公告)日：2002-09-10
申请号：US09338542
申请日：1999-06-23
申请人： Yoshihisa Nagano , Shinichiro Hayashi , Yasuhiro Uemoto
发明人： Yoshihisa Nagano , Shinichiro Hayashi , Yasuhiro Uemoto
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L28/55
摘要： A semiconductor memory includes plural lower electrodes formed on a semiconductor substrate; a capacitor dielectric film of an insulating metal oxide continuously formed over the plural lower electrodes; plural upper electrodes formed on the capacitor dielectric film in positions respectively corresponding to the plural lower electrodes; and plural transistors formed on the semiconductor substrate. The plural lower electrodes are respectively connected with source regions of the plural transistors.
摘要翻译：半导体存储器包括形成在半导体衬底上的多个下电极; 连续地形成在所述多个下电极上的绝缘金属氧化物的电容器电介质膜; 在分别对应于多个下电极的位置上形成在电容器电介质膜上的多个上电极; 以及形成在半导体基板上的多个晶体管。多个下电极分别与多个晶体管的源极区域连接。

19. 发明授权

US06333528B1 Semiconductor device having a capacitor exhibiting improved moisture resistance 失效
标题翻译：具有显示改善的耐湿性的电容器的半导体装置
公开(公告)号：US06333528B1
公开(公告)日：2001-12-25
申请号：US09071795
申请日：1998-05-04
申请人： Koji Arita , Eiji Fujii , Yasuhiro Shimada , Yasuhiro Uemoto , Toru Nasu , Akihiro Matsuda , Yoshihisa Nagano , Atsuo Inoue , Taketoshi Matsuura , Tatsuo Otsuki
发明人： Koji Arita , Eiji Fujii , Yasuhiro Shimada , Yasuhiro Uemoto , Toru Nasu , Akihiro Matsuda , Yoshihisa Nagano , Atsuo Inoue , Taketoshi Matsuura , Tatsuo Otsuki
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , H01L27/10852 , H01L27/11585 , H01L27/1159 , H01L28/40 , H01L28/55 , H01L28/60 , H01L28/75 , Y10S438/958
摘要： A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
摘要翻译：一种通过半导体衬底上的层间绝缘层形成电容器的半导体器件，其上形成集成电路。该半导体装置具有含水量为0.5g / cm 3以下的层间绝缘层，其在一个方面覆盖电容器，并且具有氢含量为1021原子/ cm3以下的钝化层，其覆盖电容器的互连在其他方面。通过这样构成，可以防止导致铁电层或高介电层的电可靠性的电容器电介质的劣化。

20. 发明授权

US06326671B1 Semiconductor memory device and method for manufacturing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06326671B1
公开(公告)日：2001-12-04
申请号：US09452620
申请日：1999-12-01
申请人： Yoshihisa Nagano , Keisuke Tanaka , Toru Nasu
发明人： Yoshihisa Nagano , Keisuke Tanaka , Toru Nasu
IPC分类号： H01L3107
CPC分类号： H01L27/11502 , H01L21/76895 , H01L27/11507 , H01L28/40
摘要： A semiconductor memory device, includes: a semiconductor substrate including a transistor; a first protective insulating film for covering the semiconductor substrate; at least one data storage capacitor element formed on the first protective insulating film; a second protective insulating film for covering the first protective insulating film and the capacitor element; a hydrogen carrier layer; and an interconnection layer for electrically connecting the transistor and the capacitor element, wherein: the capacitor element includes a lower electrode formed on the first protective insulating film, a capacitor film formed on the lower electrode, and an upper electrode formed on the capacitor film, the capacitor film includes an insulating metal oxide, the second protective insulating film has a first contact hole reaching the upper electrode and a second contact hole reaching the lower electrode, and the hydrogen barrier layer is provided in the first and second contact holes, so as not to expose the upper and the lower electrodes.
摘要翻译：一种半导体存储器件，包括：包括晶体管的半导体衬底; 用于覆盖半导体衬底的第一保护绝缘膜; 形成在所述第一保护绝缘膜上的至少一个数据存储电容器元件; 用于覆盖第一保护绝缘膜和电容器元件的第二保护绝缘膜; 氢载体层; 以及用于电连接所述晶体管和所述电容器元件的互连层，其中：所述电容器元件包括形成在所述第一保护绝缘膜上的下电极，形成在所述下电极上的电容器膜，以及形成在所述电容器膜上的上电极，电容器膜包括绝缘金属氧化物，第二保护绝缘膜具有到达上电极的第一接触孔和到达下电极的第二接触孔，并且氢阻挡层设置在第一和第二接触孔中，因此不暴露上下电极。

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