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11. 发明申请

US20120300533A1 NONVOLATILE MEMORY CELL OPERATING BY INCREASING ORDER IN POLYCRYSTALLINE SEMICONDUCTOR MATERIAL 有权
标题翻译：通过在多晶半导体材料中增加订单来操作非易失性存储器单元
公开(公告)号：US20120300533A1
公开(公告)日：2012-11-29
申请号：US13568834
申请日：2012-08-07
申请人： S. Brad Herner , Abhijit Bandyopadhyay
发明人： S. Brad Herner , Abhijit Bandyopadhyay
IPC分类号： G11C11/00 , H01L27/26 , H01L47/00
CPC分类号： G11C11/36 , G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , H01L27/1021
摘要： A memory cell is provided that includes a first conductor, a second conductor, and a semiconductor junction diode between the first and second conductors. The semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode. In addition, no resistance-switching element having its resistance changed by application of a programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor. Numerous other aspects are provided.
摘要翻译：提供了一种存储单元，其包括在第一和第二导体之间的第一导体，第二导体和半导体结二极管。半导体结二极管与半导体结二极管不与具有小于12％的晶格失配的材料接触。此外，在半导体结二极管和第一导体之间或半导体结二极管和第二导体之间设置不具有通过施加编程电压大于2的电阻而改变其电阻的电阻切换元件。提供了许多其他方面。

12. 发明申请

US20070007577A1 Integrated circuit embodying a non-volatile memory cell 审中-公开
标题翻译：集成电路体现了非易失性存储单元
公开(公告)号：US20070007577A1
公开(公告)日：2007-01-11
申请号：US11175688
申请日：2005-07-06
申请人： Abhijit Bandyopadhyay , Christopher Petti , Tanmay Kumar
发明人： Abhijit Bandyopadhyay , Christopher Petti , Tanmay Kumar
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , G11C16/0416 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： An integrated circuit is provided including at least one memory cell. Such memory cell, in turn, includes a transistor and a capacitor. The transistor includes a source, a drain, and a gate. Further, the capacitor includes a well and a gate. The gate of the transistor remains in communication with the gate of the capacitor. In various other embodiments, the memory cell includes a transistor and a capacitor including wells of differing types (e.g. P-type, N-type). In such embodiments, the well of the transistor abuts the well of the capacitor. In still further embodiments, for a more compact design, a diffusion region of the transistor is situated less than 2.5 μm from a diffusion region of the capacitor.
摘要翻译：提供了包括至少一个存储单元的集成电路。这样的存储单元又包括晶体管和电容器。晶体管包括源极，漏极和栅极。此外，电容器包括阱和栅极。晶体管的栅极保持与电容器的栅极通信。在各种其他实施例中，存储单元包括晶体管和包括不同类型的阱（例如，P型，N型）的电容器。在这样的实施例中，晶体管的阱邻接电容器的阱。在另外的实施例中，为了更紧凑的设计，晶体管的扩散区域距离电容器的扩散区域小于2.5μm。

13. 发明授权

US08520424B2 Composition of memory cell with resistance-switching layers 有权
标题翻译：具有电阻切换层的存储单元的组成
公开(公告)号：US08520424B2
公开(公告)日：2013-08-27
申请号：US13157204
申请日：2011-06-09
申请人： Franz Kreupl , Abhijit Bandyopadhyay , Yung-Tin Chen , Chu-Chen Fu , Wipul Pemsiri Jayasekara , James Kai , Raghuveer S. Makala , Peter Rabkin , George Samachisa , Jingyan Zhang
发明人： Franz Kreupl , Abhijit Bandyopadhyay , Yung-Tin Chen , Chu-Chen Fu , Wipul Pemsiri Jayasekara , James Kai , Raghuveer S. Makala , Peter Rabkin , George Samachisa , Jingyan Zhang
IPC分类号： G11C11/00
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。第一和第二电阻切换层都可以具有双极或单极开关特性。在存储单元的置位或复位操作中，离子电流在电阻切换层中流动，有助于切换机构。由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。提供了用于RSME不同层的材料和材料的组合。

14. 发明授权

US08289749B2 Soft forming reversible resistivity-switching element for bipolar switching 有权
标题翻译：用于双极开关的软成型可逆电阻率开关元件
公开(公告)号：US08289749B2
公开(公告)日：2012-10-16
申请号：US12642191
申请日：2009-12-18
申请人： Xiying Chen , Abhijit Bandyopadhyay , Brian Le , Roy Scheuerlein , Li Xiao
发明人： Xiying Chen , Abhijit Bandyopadhyay , Brian Le , Roy Scheuerlein , Li Xiao
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2013/0092 , G11C2213/32 , G11C2213/34
摘要： A method and system for forming reversible resistivity-switching elements is described herein. Forming refers to reducing the resistance of the reversible resistivity-switching element, and is generally understood to refer to reducing the resistance for the first time. Prior to forming the reversible resistivity-switching element it may be in a high-resistance state. A first voltage is applied to “partially form” the reversible resistivity-switching element. The first voltage has a first polarity. Partially forming the reversible resistivity-switching element lowers the resistance of the reversible resistivity-switching element. A second voltage that has the opposite polarity as the first is then applied to the reversible resistivity-switching element. Application of the second voltage may further lower the resistance of the reversible resistivity-switching element. Therefore, the second voltage could be considered as completing the forming of the reversible resistivity-switching element.
摘要翻译：本文描述了用于形成可逆电阻率开关元件的方法和系统。形成是指降低可逆电阻率开关元件的电阻，并且通常被理解为指第一次降低电阻。在形成可逆电阻率开关元件之前，它可能处于高电阻状态。施加第一电压以部分地形成可逆电阻率开关元件。第一电压具有第一极性。部分形成可逆电阻率开关元件降低可逆电阻率开关元件的电阻。然后将具有与第一相反极性的第二电压施加到可逆电阻率开关元件。第二电压的施加可以进一步降低可逆电阻率开关元件的电阻。因此，可以将第二电压视为完成可逆电阻率开关元件的形成。

15. 发明授权

US07888205B2 Highly scalable thin film transistor 有权
标题翻译：高度可扩展的薄膜晶体管
公开(公告)号：US07888205B2
公开(公告)日：2011-02-15
申请号：US12659480
申请日：2010-03-10
申请人： S. Brad Herner , Abhijit Bandyopadhyay
发明人： S. Brad Herner , Abhijit Bandyopadhyay
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11578
摘要： Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse into the channel, potentially shorting it and ruining the device. A suite of innovations is described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor, resulting in a highly scalable thin film transistor. This transistor is particularly suitable for use in a monolithic three dimensional array of stacked device levels.
摘要翻译： PMOS或NMOS薄膜晶体管的尺寸缩小受掺杂剂扩散的限制。在这些器件中，未掺杂或轻掺杂的沟道区被插入在重掺杂的源极和漏极区之间。当器件以非常短的栅极长度构建时，源极和漏极掺杂物将扩散到沟道中，从而潜在地短路并破坏器件。描述了一组创新，其可以以各种组合使用，以在制造PMOS或NMOS多晶薄膜晶体管期间最小化掺杂剂扩散，导致高度可缩放的薄膜晶体管。该晶体管特别适用于堆叠器件级的单片三维阵列。

16. 发明申请

US20060221758A1 TRANSISTOR LAYOUT CONFIGURATION FOR TIGHT-PITCHED MEMORY ARRAY LINES 有权
标题翻译：用于紧凑的内存阵列的晶体管布局配置
公开(公告)号：US20060221758A1
公开(公告)日：2006-10-05
申请号：US11420787
申请日：2006-05-29
申请人： Christopher Petti , Roy Scheuerlein , Tanmay Kumar , Abhijit Bandyopadhyay
发明人： Christopher Petti , Roy Scheuerlein , Tanmay Kumar , Abhijit Bandyopadhyay
IPC分类号： G11C8/00
CPC分类号： G11C8/14 , G11C5/02 , G11C5/063 , G11C8/08 , H01L27/0207 , H01L27/0688 , H01L27/10894 , H01L27/10897
摘要： A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line. In certain embodiments, a respective plurality of complementary array line driver circuits is disposed on each side of a connection area between adjacent memory blocks, and each such driver circuit is responsive to a single driver input node.
摘要翻译：多头字线驱动电路包括弯栅晶体管，以减少为了与紧密排列的阵列线连接而实现的间距。在某些示例性实施例中，三维存储器阵列包括穿过至少一个存储器块水平横越的多个存储器块和阵列线。垂直有源区条纹设置在第一存储块下方，并且相应的多个弯曲栅电极与每个相应的有源区条纹相交以限定各个源/漏区。每个其它源极/漏极区域耦合到用于有源区域条纹的偏置节点，并且剩余的源极/漏极区域分别耦合到与第一存储器模块相关联的相应阵列线，从而形成用于相应阵列的相应的第一驱动器晶体管线。在某些实施例中，相应的多个互补阵列线驱动器电路设置在相邻存储块之间的连接区域的每一侧上，并且每个这样的驱动器电路响应于单个驱动器输入节点。

17. 发明授权

US08624293B2 Carbon/tunneling-barrier/carbon diode 有权
标题翻译：碳/隧道势垒/碳二极管
公开(公告)号：US08624293B2
公开(公告)日：2014-01-07
申请号：US12639840
申请日：2009-12-16
申请人： Abhijit Bandyopadhyay , Franz Kreupl , Andrei Mihnea , Li Xiao
发明人： Abhijit Bandyopadhyay , Franz Kreupl , Andrei Mihnea , Li Xiao
IPC分类号： H01L29/66
CPC分类号： H01L45/00 , H01L27/2418 , H01L27/2463 , H01L29/16 , H01L29/88
摘要： A carbon/tunneling-barrier/carbon diode and method for forming the same are disclosed. The carbon/tunneling-barrier/carbon may be used as a steering element in a memory array. Each memory cell in the memory array may include a reversible resistivity-switching element and a carbon/tunneling-barrier/carbon diode as the steering element. The tunneling-barrier may include a semiconductor or an insulator. Thus, the diode may be a carbon/semiconductor/carbon diode. The semiconductor in the diode may be intrinsic or doped. The semiconductor may be depleted when the diode is under equilibrium conditions. For example, the semiconductor may be lightly doped such that the depletion region extends from one end of the semiconductor region to the other end. The diode may be a carbon/insulator/carbon diode.
摘要翻译：公开了一种碳/隧道势垒/碳二极管及其形成方法。碳/隧道势垒/碳可以用作存储器阵列中的转向元件。存储器阵列中的每个存储单元可以包括可逆电阻率开关元件和作为转向元件的碳/隧道势垒/碳二极管。隧道势垒可以包括半导体或绝缘体。因此，二极管可以是碳/半导体/碳二极管。二极管中的半导体可以是固有的或掺杂的。当二极管处于平衡条件下时，半导体可能耗尽。例如，半导体可以被轻掺杂，使得耗尽区从半导体区的一端延伸到另一端。二极管可以是碳/绝缘体/碳二极管。

18. 发明授权

US08520425B2 Resistive random access memory with low current operation 有权
标题翻译：具有低电流运行的电阻式随机存取存储器
公开(公告)号：US08520425B2
公开(公告)日：2013-08-27
申请号：US13424131
申请日：2012-03-19
申请人： Li Xiao , Chandu Gorla , Abhijit Bandyopadhyay , Andrei Mihnea
发明人： Li Xiao , Chandu Gorla , Abhijit Bandyopadhyay , Andrei Mihnea
IPC分类号： G11C11/00 , G11C13/0002
CPC分类号： G11C13/0007 , G11C5/02 , G11C8/10 , G11C13/0023 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2013/0083 , G11C2213/32 , G11C2213/33 , G11C2213/71 , G11C2213/72 , G11C2213/76 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： A memory cell in a 3-D read and write memory device has two bipolar resistance-switching layers with different respective switching currents. A low current resistance-switching layer can be switched in set and reset processes while a high current resistance-switching layer remains in a reset state and acts as a protection resistor to prevent excessively high currents on the low current resistance-switching layer. The low and high current resistance-switching layers can be of the same material such as a metal oxide, where the layers differ in terms of thickness, doping, leakiness, metal richness or other variables. Or, the low and high current resistance-switching layers can be of different materials, having one or more layers each. The high current resistance-switching layer can have a switching current which is greater than a switching current of the low current resistance-switching layer by a factor of at least 1.5 or 2.0, for instance.
摘要翻译： 3-D读写存储器件中的存储单元具有两个具有不同开关电流的双极性电阻切换层。低电流电阻切换层可以在置位和复位过程中被切换，而高电流电阻切换层保持复位状态，并且作为保护电阻来防止低电流电阻切换层上的过大电流。低电流和高电流电阻切换层可以是相同的材料，例如金属氧化物，其中层的厚度，掺杂，泄漏，金属浓度等变化不同。或者，低电流和高电流电阻切换层可以是不同的材料，每个具有一个或多个层。高电流电阻切换层例如可以具有比低电流电阻切换层的开关电流大至少1.5或2.0的开关电流。

19. 发明授权

US08385102B2 Alternating bipolar forming voltage for resistivity-switching elements 有权
标题翻译：用于电阻率开关元件的交替双极形成电压
公开(公告)号：US08385102B2
公开(公告)日：2013-02-26
申请号：US12949590
申请日：2010-11-18
申请人： Li Xiao , Abhijit Bandyopadhyay , Tao Du
发明人： Li Xiao , Abhijit Bandyopadhyay , Tao Du
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2013/0092 , G11C2213/32 , G11C2213/72
摘要： A method and system for forming reversible resistivity-switching elements is described herein. Forming refers to reducing the resistance of the reversible resistivity-switching element, and may refer to reducing the resistance for the first time. Prior to forming the reversible resistivity-switching element it may be in a high-resistance state. The method may comprise alternating between applying one or more first voltages having a first polarity to the memory cell and applying one or more second voltages having a second polarity that is opposite the first polarity to the memory cell until the reversible resistivity-switching memory element is formed. There may be a rest period between applying the voltages of opposite polarity.
摘要翻译：本文描述了用于形成可逆电阻率开关元件的方法和系统。形成是指降低可逆电阻率开关元件的电阻，并且可以指第一次降低电阻。在形成可逆电阻率开关元件之前，它可能处于高电阻状态。该方法可以包括在向存储器单元施加具有第一极性的一个或多个第一电压并且向存储器单元施加具有与第一极性相反的第二极性的一个或多个第二电压，直到可逆电阻率切换存储元件为形成。在施加相反极性的电压之间可能有一个休息时间。

20. 发明授权

US08243509B2 Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material 有权
标题翻译：非易失性存储单元通过增加多晶半导体材料的顺序来操作
公开(公告)号：US08243509B2
公开(公告)日：2012-08-14
申请号：US13074509
申请日：2011-03-29
申请人： S. Brad Herner , Abhijit Bandyopadhyay
发明人： S. Brad Herner , Abhijit Bandyopadhyay
IPC分类号： G11C11/36 , G11C11/34 , G11C11/00
CPC分类号： G11C11/36 , G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , H01L27/1021
摘要： A nonvolatile memory cell is described, the memory cell comprising a semiconductor diode. The semiconductor material making up the diode is formed with significant defect density, and allows very low current flow at a typical read voltage. Application of a programming voltage permanently changes the nature of the semiconductor material, resulting in an improved diode. The programmed diode allows much higher current flow, in some embodiments one, two or three orders of magnitude higher, at the same read voltage. The difference in current allows a programmed memory cell to be distinguished from an unprogrammed memory cell. Fabrication techniques to generate an advantageous unprogrammed defect density are described. The memory cell of the present invention can be formed in a monolithic three dimensional memory array, having multiple stacked memory levels formed above a single substrate.
摘要翻译：描述非易失性存储单元，存储单元包括半导体二极管。构成二极管的半导体材料形成有明显的缺陷密度，并且在典型的读取电压下允许非常低的电流流动。编程电压的应用永久地改变了半导体材料的性质，导致改进的二极管。在相同的读取电压下，编程的二极管允许更高的电流流动，在一些实施例中高一个，两个或三个数量级。电流差异允许将编程的存储器单元与未编程的存储器单元进行区分。描述了产生有利的未编程缺陷密度的制造技术。本发明的存储单元可以形成为在单个衬底上形成多个堆叠存储器级的单片三维存储器阵列。

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