专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US11048516B2 Systems, methods, and apparatuses for last branch record support compatible with binary translation and speculative execution using an architectural bit array and a write bit array 有权
公开(公告)号：US11048516B2
公开(公告)日：2021-06-29
申请号：US14752891
申请日：2015-06-27
申请人： Paul Caprioli , Koichi Yamada , Jason M. Agron , Jiwei Lu
发明人： Paul Caprioli , Koichi Yamada , Jason M. Agron , Jiwei Lu
IPC分类号： G06F9/38 , G06F9/30
摘要： Systems, methods, and apparatuses for last branch record support are described. In an embodiment, a hardware processor core comprises a hardware execution unit to execute a branch instruction, at least two last branch record (LBR) registers to store a source and destination information of a branch taken during program execution, wherein an entry in a LBR register is to include an encoding of the branch, a write bit array to indicate which LBR register is architecturally correct, an architectural bit array to indicate when an LBR register has been written, and a plurality of top of stack pointers to indicate which LBR register in a LBR register stack is to be written.

12. 发明申请

US20180349603A1 System, Apparatus And Method For Instruction Level Behavioral Analysis Without Binary Instrumentation 审中-公开
公开(公告)号：US20180349603A1
公开(公告)日：2018-12-06
申请号：US15609369
申请日：2017-05-31
申请人： Koichi Yamada , Tugrul Ince , Paul A. Campbell , Jiunn-Yeu Chen
发明人： Koichi Yamada , Tugrul Ince , Paul A. Campbell , Jiunn-Yeu Chen
IPC分类号： G06F21/56 , G06F21/55
CPC分类号： G06F21/566 , G06F21/554
摘要： In one embodiment, an apparatus includes an execution monitor to monitor an application in execution, identify a code region, generate region information for the code region, and analyze the code region to identify potential malicious behavior, and if the potential malicious behavior is identified, to alert a security agent, and otherwise to enable the code region to execute, where the execution monitor is isolated from the application. Other embodiments are described and claimed.

13. 发明授权

US08688951B2 Operating system virtual memory management for hardware transactional memory 有权
标题翻译：硬件事务内存的操作系统虚拟内存管理
公开(公告)号：US08688951B2
公开(公告)日：2014-04-01
申请号：US13554558
申请日：2012-07-20
申请人： Koichi Yamada , Gad Sheaffer , Ali-Reza Adl-Tabatabai , Landy Wang , Martin Taillefer , Arun Kishan , David Callahan , Jan Gray , Vadim Bassin
发明人： Koichi Yamada , Gad Sheaffer , Ali-Reza Adl-Tabatabai , Landy Wang , Martin Taillefer , Arun Kishan , David Callahan , Jan Gray , Vadim Bassin
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/26 , G06F9/34 , G06F9/455 , G06F9/46
CPC分类号： G06F12/1045 , G06F12/0815
摘要： Operating system virtual memory management for hardware transactional memory. A system includes an operating system deciding to unmap a first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode. Embodiments may further perform soft page fault handling without aborting a hardware transaction, resuming the hardware transaction upon return to user mode, and even successfully committing the hardware transaction.
摘要翻译：硬件事务内存的操作系统虚拟内存管理。系统包括决定取消映射第一虚拟页面的操作系统。结果，操作系统从虚拟存储器页表移除第一虚拟页面到第一物理页面的映射。结果，操作系统执行至少第一物理页丢弃事务存储器硬件状态的动作。实施例可以进一步挂起内核模式下的硬件事务。实施例可以进一步执行软页错误处理，而不中止硬件事务，在返回到用户模式时恢复硬件事务，甚至成功地提交硬件事务。

14. 发明授权

US08521995B2 Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode 有权
标题翻译：以无界事务内存（UTM）模式处理操作系统（OS）转换
公开(公告)号：US08521995B2
公开(公告)日：2013-08-27
申请号：US12638064
申请日：2009-12-15
申请人： Koichi Yamada , Gad Sheaffer , Jan Gray , Landy Wang , Martin Taillefer , Arun Kishan , Ali-Reza Adl-Tabatabai , David Callahan
发明人： Koichi Yamada , Gad Sheaffer , Jan Gray , Landy Wang , Martin Taillefer , Arun Kishan , Ali-Reza Adl-Tabatabai , David Callahan
IPC分类号： G06F13/14
CPC分类号： G06F9/3834 , G06F9/30076 , G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F9/461 , G06F9/467 , G06F9/4812 , G06F2209/481
摘要： A method includes receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread.
摘要翻译：一种方法包括：在执行无界事务存储器（UTM）事务期间，通过来自用户线程的环转移接收控制，更新与用户线程相关联的事务状态寄存器（TSR）的状态并将TSR与用户线程的上下文，然后在从内核模式到用户线程的转换期间恢复上下文。以这种方式，UTM事务可以继续恢复用户线程。

15. 发明授权

US08213029B2 Apparatus, method, and program for editing images for a photo album 有权
标题翻译：用于编辑相册的图像的装置，方法和程序
公开(公告)号：US08213029B2
公开(公告)日：2012-07-03
申请号：US13111994
申请日：2011-05-20
申请人： Takashi Tsue , Koichi Yamada , Kazuhiro Mino
发明人： Takashi Tsue , Koichi Yamada , Kazuhiro Mino
IPC分类号： G06F15/00 , G06F3/12 , G06K1/00
CPC分类号： H04N1/00442 , H04N1/00145 , H04N1/00164 , H04N1/00167 , H04N1/00183 , H04N1/00188 , H04N1/00196 , H04N1/00448 , H04N1/00456 , H04N1/00458 , H04N1/00461 , H04N1/00482
摘要： For generating photo albums on events such as weddings, the photo albums can always be generated in the same quality. A professional photographer photographs the bride and groom on a wedding. Images are read from a developed film and stored in a file server. A template used for generating a photo album is added with composition information representing composition of images to be inserted in image insertion areas therein. When an operator selects one of the images to be inserted in any one of the image insertion areas with reference to an editing screen having a catalog display field and a template display field, processing information representing a magnification ratio and/or a trimming position is generated based on the composition information so that the selected image has the composition appropriate for the image insertion area. The selected image is processed according to the processing information.
摘要翻译：为了在诸如婚礼等事件上生成相册，相册始终可以以相同的质量生成。专业摄影师在婚礼上拍摄新娘和新郎。图像从开发的胶片读取并存储在文件服务器中。添加了用于生成相册的模板，其中组合信息表示要插入其中的图像插入区域中的图像的组合。参照具有目录显示区域和模板显示区域的编辑画面，当操作者选择要插入到任一个图像插入区域中的一个图像时，生成表示放大率和/或修剪位置的处理信息基于所述构图信息，使得所选择的图像具有适合于图像插入区域的构图。所选择的图像根据处理信息被处理。

16. 发明授权

US07675647B2 Apparatus, method, and program for editing images 有权
标题翻译：用于编辑图像的装置，方法和程序
公开(公告)号：US07675647B2
公开(公告)日：2010-03-09
申请号：US10998142
申请日：2004-11-29
申请人： Takashi Tsue , Koichi Yamada , Akira Yoda
发明人： Takashi Tsue , Koichi Yamada , Akira Yoda
IPC分类号： G06F15/00
CPC分类号： H04N1/0035 , G06T11/60 , H04N1/00183 , H04N1/00196 , H04N1/00198 , H04N1/00448 , H04N1/00458
摘要： When a photo album on an event such as wedding is generated, images to be inserted in image insertion areas in a template can be selected easily. A professional photographer photographs the bride and groom on the day of wedding, and obtains images. Characteristic quantities of scenes represented by the images are calculated, and the images are classified into image groups of the scenes. With reference to a reference-value sequence table describing reference values of the characteristic quantities of the scenes in the event in order of occurrence of the scenes, the image groups are arranged in order of the scene occurrence. A catalog of the images is generated in the same order, and displayed in an editing screen.
摘要翻译：当生成诸如婚礼的事件的相册时，可以容易地选择要插入到模板中的图像插入区域中的图像。专业摄影师在婚礼当天拍摄新娘和新郎，并获得图像。计算由图像表示的特征量的场景，并将图像分类为场景的图像组。参考以场景发生的顺序来描述场景的特征量的参考值的参考值序列表，按照场景发生的顺序排列图像组。图像的目录以相同的顺序生成，并显示在编辑屏幕中。

17. 发明授权

US07587639B2 System and method for error injection using a flexible program interface field 有权
标题翻译：使用灵活的程序接口字段进行错误注入的系统和方法
公开(公告)号：US07587639B2
公开(公告)日：2009-09-08
申请号：US10985502
申请日：2004-11-09
申请人： Suresh K. Marisetty , Rajendra Kuramkote , Koichi Yamada , Scott D. Brenden , Kushagra V. Vaid
发明人： Suresh K. Marisetty , Rajendra Kuramkote , Koichi Yamada , Scott D. Brenden , Kushagra V. Vaid
IPC分类号： G06F11/00
CPC分类号： G06F11/3672
摘要： A system and method for injecting hardware errors into a microprocessor system is described. In one embodiment, a software interface between system software and system firmware is established. Software test and debug for software error handlers may thus be supported. The software interface may support both a query mode call and a seed mode call. When a query mode call is issued, it may request whether or not the system firmware and hardware support the injection of a specified kind of error. A return from this call may be used to make a list of supported errors for injection. When a seed mode call is issued, the corresponding error may be injected into the hardware.
摘要翻译：描述了将硬件错误注入微处理器系统的系统和方法。在一个实施例中，建立了系统软件和系统固件之间的软件接口。因此可以支持软件错误处理程序的软件测试和调试。软件界面可以支持查询模式呼叫和种子模式呼叫。发出查询模式呼叫时，可以请求系统固件和硬件是否支持注入指定类型的错误。此呼叫的返回可用于列出支持的注入错误。当发出种子模式呼叫时，相应的错误可能会被注入到硬件中。

18. 发明申请

US20090007121A1 Method And Apparatus To Enable Runtime Processor Migration With Operating System Assistance 有权
标题翻译：使用操作系统协助启用运行时处理器迁移的方法和装置
公开(公告)号：US20090007121A1
公开(公告)日：2009-01-01
申请号：US11772155
申请日：2007-06-30
申请人： Koichi Yamada , Douglas E. Covelli , Jose A. Vargas , Mohan J. Kumar
发明人： Koichi Yamada , Douglas E. Covelli , Jose A. Vargas , Mohan J. Kumar
IPC分类号： G06F9/46
CPC分类号： G06F11/2028 , G06F11/203 , G06F11/2051
摘要： In a method for switching to a spare processor during runtime, a processing system determines that execution should be migrated off of an active processor. An operating system (OS) scheduler and at least one device are then paused, and the active processor is put into an idle state. State data from writable and substantial non-writable stores in the active processor is loaded into the spare processor. Interrupt routing table logic for the processing system is dynamically reprogrammed to direct external interrupts to the spare processor. The active processor may then be off-lined, and the device and OS scheduler may be unpaused or resumed. Threads may then be dispatched to the spare processor for execution. Other embodiments are described and claimed.
摘要翻译：在运行时切换到备用处理器的方法中，处理系统确定执行应当从有源处理器迁移。然后暂停操作系统（OS）调度器和至少一个设备，并且活动处理器进入空闲状态。有源处理器中的可写和基本不可写存储器的状态数据被加载到备用处理器中。用于处理系统的中断路由表逻辑被动态重新编程，以将外部中断引导到备用处理器。然后，活动处理器可以被排除在外，并且设备和OS调度器可以被取消启动或恢复。然后可以将线程分派到备用处理器执行。描述和要求保护其他实施例。

19. 发明申请

US20070005932A1 Memory management in a multiprocessor system 审中-公开
标题翻译：多处理器系统中的内存管理
公开(公告)号：US20070005932A1
公开(公告)日：2007-01-04
申请号：US11169412
申请日：2005-06-29
申请人： Douglas Covelli , William Cheung , Koichi Yamada
发明人： Douglas Covelli , William Cheung , Koichi Yamada
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/652 , G06F2212/682
摘要： Embodiments of memory management in a multiprocessor system are disclosed. Embodiments include a system and method for maintaining translation lookaside buffer (TLB) consistency or coherency in a multiprocessor system. A coalescing component receives from a host system a list of TLB pages to be invalidated or purged. The coalescing component uses information of the TLB invalidation broadcast mechanism in use by a processor in the multiprocessor system to evaluate the list of TLB pages. The coalescing component generates a single TLB invalidation message with a variable invalidation range to cover multiple TLB pages of the list or the entire list of TLB pages to be invalidated, and the invalidation message is used to invalidate multiple TLB pages on multiple processors of the host system. Other embodiments are described and claimed.
摘要翻译：公开了多处理器系统中的存储器管理的实施例。实施例包括用于在多处理器系统中维持翻译后备缓冲器（TLB）一致性或一致性的系统和方法。合并组件从主机系统接收将被无效或清除的TLB页面的列表。合并组件使用多处理器系统中的处理器使用的TLB无效广播机制的信息来评估TLB页面的列表。合并组件生成具有可变无效范围的单个TLB无效消息，以覆盖该列表的多个TLB页面或将要被无效的TLB页面的整个列表，并且使用无效消息来使主机的多个处理器上的多个TLB页面无效系统。描述和要求保护其他实施例。

20. 发明申请

US20060069899A1 Performance enhancement of address translation using translation tables covering large address spaces 有权
标题翻译：使用涵盖大地址空间的翻译表进行地址转换的性能提升
公开(公告)号：US20060069899A1
公开(公告)日：2006-03-30
申请号：US10957306
申请日：2004-09-30
申请人： Ioannis Schoinas , Gilbert Neiger , Rajesh Madukkarumukumana , Ku-jei King , Richard Uhlig , Achmed Zahir , Koichi Yamada
发明人： Ioannis Schoinas , Gilbert Neiger , Rajesh Madukkarumukumana , Ku-jei King , Richard Uhlig , Achmed Zahir , Koichi Yamada
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F12/1036 , G06F12/109
摘要： An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.
摘要翻译：本发明的一个实施例是一种增强地址转换性能的技术。寄存器存储用于指示由芯片组中的电路支持的能力指示符，用于将客体物理地址地址转换为主机物理地址。在地址转换中使用多个多级页表进行页面行走。每个页表都有页表项。每个页表条目至少具有与能力指示符指示的能力对应的条目说明符。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式