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11. 发明授权

US07122888B2 Semiconductor device, electrical inspection method thereof, and electronic apparatus including the semiconductor device 有权
标题翻译：半导体装置及其电气检查方法以及包括该半导体装置的电子设备
公开(公告)号：US07122888B2
公开(公告)日：2006-10-17
申请号：US11091851
申请日：2005-03-29
申请人： Ichiro Egawa , Yukihisa Orisaka
发明人： Ichiro Egawa , Yukihisa Orisaka
IPC分类号： H01L29/00 , H01L23/52 , H01L23/34
CPC分类号： G09G3/006 , G09G3/3677 , G09G3/3688 , G09G2310/0283 , H01L22/32 , H01L2224/73204 , H01L2924/07811 , H01L2924/3011 , H05K1/0231 , H05K1/189 , Y10S257/924 , H01L2924/00
摘要： A semiconductor device is arranged so as to include (i) a wire L1, connected directly to an LSI chip, which serves as a VGL wire for supplying a voltage VGL to the LSI chip, and (ii) a wire LB1 connected not directly to but to one of a pair of electrodes of a capacitor provided between the wire LB1 and a voltage VGH wire, each of the wire L1 and the wire LB1 including a voltage input terminal. This arrangement provides (i) a semiconductor device, including a built-in capacitor, which makes it possible to shorten time required in an electrical screening test (final test) so as to reduce cost, and (ii) an electrical inspection method of the semiconductor device.
摘要翻译：半导体器件被布置为包括（i）直接连接到LSI芯片的线L1，其用作用于向LSI芯片提供电压VGL的VGL线，以及（ii）未连接的线LB1 直接连接到设置在线LB1和电压VGH线之间的电容器的一对电极中的一个，线L1和线LB1中的每一个包括电压输入端子。这种布置提供（i）包括内置电容器的半导体器件，其可以缩短电气筛选测试（最终测试）所需的时间，从而降低成本，以及（ii）电气检查方法半导体器件。

12. 发明授权

US5325411A Display driving circuit 失效
标题翻译：显示驱动电路
公开(公告)号：US5325411A
公开(公告)日：1994-06-28
申请号：US27765
申请日：1993-03-08
申请人： Yukihisa Orisaka
发明人： Yukihisa Orisaka
IPC分类号： G09G3/20 , G09G3/36 , H03K21/02 , H03K21/08
CPC分类号： G09G3/3685
摘要： A display driving circuit includes a latch circuit provided with a resetting terminal for receiving a pulse signal having a constant period and a setting terminal, a logic product circuit for receiving an output signal of the latch circuit and the pulse signal, a counting circuit having a resetting terminal for receiving an output signal of the logic product circuit and a counting terminal for receiving a clock signal, the counting circuit outputting a data pulse every time a number of pulses of the clock signals reaches a preset constant value from a reception of the output signal of the logic product circuit; and a shift register for receiving the data pulse of the counting circuit at a data signal input terminal thereof and receiving the clock signal at a clock input terminal thereof, the latch circuit being adapted to receive the data pulse of the counting circuit at said setting terminal thereof.
摘要翻译：显示驱动电路包括：锁存电路，具有用于接收具有恒定周期的脉冲信号的复位端子和设定端子，用于接收锁存电路的输出信号的逻辑积电路和脉冲信号;计数电路，具有用于接收逻辑积电路的输出信号的复位端子和用于接收时钟信号的计数端子，所述计数电路每当从输出的接收到的时钟信号的数量的脉冲达到预设的常数值时，输出数据脉冲逻辑产品电路的信号; 以及移位寄存器，用于在其数据信号输入端接收计数电路的数据脉冲，并在其时钟输入端接收时钟信号，该锁存电路适于在所述设置端接收计数电路的数据脉冲其中。

13. 发明授权

US5317203A Sample-and-hold circuit 失效
标题翻译：采样和保持电路
公开(公告)号：US5317203A
公开(公告)日：1994-05-31
申请号：US872160
申请日：1992-04-22
申请人： Junji Tanaka , Toshio Watanabe , Yukihisa Orisaka
发明人： Junji Tanaka , Toshio Watanabe , Yukihisa Orisaka
IPC分类号： G11C27/02
CPC分类号： G11C27/026
摘要： Disclosed is a sample-and-hold circuit. A plurality of input signals are applied to the capacitors through the corresponding analog switches. The capacitors are charged to the instantaneous voltages of input signals when the corresponding analog switches are conducting. An output circuit comprising a plurality of input circuit legs and an output is provided. Each input circuit leg includes series connected input transistor and switching transistor. Input circuit legs are connected in parallel. A plurality of inputs of the switching trainsistors are supplied with input switching signals to turn on the switching transistors in a systematic chosen sequence. And a plurality of inputs of the input transisntrs are connected to the capacitors to put the voltage across one of the capacitors to the output during the time when the corresponding analog switch is in the hold mode and the corresponding switch transisor is conducting.
摘要翻译：公开了采样保持电路。通过相应的模拟开关将多个输入信号施加到电容器。当相应的模拟开关导通时，电容器被充电到输入信号的瞬时电压。提供包括多个输入电路支路和输出的输出电路。每个输入电路支路包括串联连接的输入晶体管和开关晶体管。输入电路脚并联。切换列车电阻器的多个输入端被提供有输入切换信号，以系统选择的顺序接通开关晶体管。并且输入转换器的多个输入端连接到电容器，以在相应的模拟开关处于保持模式并且相应的开关转换器导通的时间期间将电压跨过电容器之一施加到输出端。

14. 发明授权

US5289063A Output circuit with buffer 失效
标题翻译：输出电路带缓冲器
公开(公告)号：US5289063A
公开(公告)日：1994-02-22
申请号：US960872
申请日：1992-10-14
申请人： Yukihisa Orisaka , Junji Tanaka , Yoshiki Sano
发明人： Yukihisa Orisaka , Junji Tanaka , Yoshiki Sano
IPC分类号： H03K17/16 , H03K17/04 , H03K17/687 , H03K19/017 , H03K19/0175 , H03K19/096
CPC分类号： H03K19/096 , H03K19/01742
摘要： An output circuit having a buffer, the buffer including the first transistor which receives at a gate thereof a periodic input voltage and the second transistor, the first and the second transistors being connected in series across a power line and a ground line, a junction of the first and second transistors being connected to an output terminal. The output circuit includes a circuit for applying, to a gate of the second transistor, a first voltage for the second transistor to serve as a bias transistor for charging a load connected to the output terminal with a voltage corresponding to the input voltage, and the second voltage greater than the first voltage for the second transistor to serve as a discharge transistor for discharging the load.
摘要翻译：一种具有缓冲器的输出电路，所述缓冲器包括在其栅极处接收周期性输入电压的第一晶体管和所述第二晶体管，所述第一和第二晶体管串联连接在电源线和接地线上，第一和第二晶体管连接到输出端子。输出电路包括用于向第二晶体管的栅极施加用于第二晶体管的第一电压以用作用于以与输入电压相对应的电压对连接到输出端子的负载充电的偏置晶体管的电路，大于第二晶体管的第一电压的第二电压用作用于放电负载的放电晶体管。

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