专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20130052837A1 Apparatus and Methods for Annealing Wafers 有权
标题翻译：退火晶圆的设备和方法
公开(公告)号：US20130052837A1
公开(公告)日：2013-02-28
申请号：US13215909
申请日：2011-08-23
申请人： Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
发明人： Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
IPC分类号： H01L21/268 , B23K26/00
CPC分类号： H01L21/67115 , B23K26/352 , H01L21/2636 , H01L21/268 , H01L21/324
摘要： A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.
摘要翻译：一种方法包括在晶片上进行退火。晶片包括晶片边缘区域和由晶片边缘区域包围的内部区域。在退火期间，施加在晶片边缘区域的一部分上的第一功率至少低于用于退火内部区域的第二功率。

12. 发明申请

US20100320913A1 LIGHT EMITTING DIODE (LED) MODULE WITH TIME DELAY FUNCTION 审中-公开
标题翻译：具有时间延迟功能的发光二极管（LED）模块
公开(公告)号：US20100320913A1
公开(公告)日：2010-12-23
申请号：US12488574
申请日：2009-06-21
申请人： Long Wu , Jian-Fuh Chen , Yu-Chang Lin
发明人： Long Wu , Jian-Fuh Chen , Yu-Chang Lin
IPC分类号： H05B37/00
CPC分类号： H05B33/0815 , H02J9/065 , H05B33/0803 , Y02B20/383
摘要： The present invention provides a light emitting diode LED module with a time-delay lighting function, having an LED light-emitting unit on the power input circuit. The power input circuit for the LED light-emitting unit is connected with main power supply, backup power supply and backup power controller. The backup power supply and LED light-emitting unit are connected in parallel. At least two circuits are formed at the output end of the main power supply, one of which is connected with LED light-emitting unit for power supply and lighting purpose, and the other one of which is connected with the backup power supply via the backup power controller, allowing for charging/discharging of the backup power supply.
摘要翻译：本发明提供一种具有时间延迟照明功能的发光二极管LED模块，在电源输入电路上具有LED发光单元。 LED发光单元的电源输入电路与主电源，备用电源和备用电源控制器相连。备用电源和LED发光单元并联。在主电源的输出端形成至少两个电路，其中一个电路与用于电源和照明目的的LED发光单元连接，另一个电路通过备用电源与备用电源连接电源控制器，允许备用电源的充电/放电。

13. 发明授权

US07439751B2 Apparatus and method for testing conductive bumps 有权
标题翻译：用于测试导电凸块的装置和方法
公开(公告)号：US07439751B2
公开(公告)日：2008-10-21
申请号：US11527696
申请日：2006-09-27
申请人： Yian-Liang Kuo , Yu-Chang Lin , Yu-Ting Lin
发明人： Yian-Liang Kuo , Yu-Chang Lin , Yu-Ting Lin
IPC分类号： G01R31/02
CPC分类号： G01R1/07307 , G01R31/046 , G01R31/2896
摘要： An apparatus and method for testing conductive bumps are provided. An exemplary embodiment of a bump testing unit comprises a support substrate with two probes protruding one surface thereof. A digital detecting device is embedded in the support substrate, comprising a first and second input terminals and an output terminal, wherein the input terminals electrically connects one of the probes.
摘要翻译：提供一种用于测试导电凸块的装置和方法。凸块测试单元的示例性实施例包括具有两个探针突出在其一个表面上的支撑基板。数字检测装置嵌入在支撑基板中，包括第一和第二输入端子和输出端子，其中输入端子电连接其中一个探针。

14. 发明授权

US07348596B2 Devices for detecting current leakage between deep trench capacitors in DRAM devices 有权
标题翻译：用于检测DRAM器件中深沟槽电容器之间的电流泄漏的装置
公开(公告)号：US07348596B2
公开(公告)日：2008-03-25
申请号：US10979609
申请日：2004-11-02
申请人： Yu-Chang Lin
发明人： Yu-Chang Lin
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , G11C11/401 , G11C29/006 , G11C29/50 , G11C2029/5006 , H01L22/34 , H01L27/10861
摘要： A test device for detecting current leakage between deep trench capacitors in DRAM devices. The test device is disposed in a scribe line region of a wafer. In the test device, a first trench capacitor pair has a first deep trench capacitor and a second deep trench capacitor connected in parallel. A first transistor has a first terminal electrically coupled to the first deep trench capacitor and a control terminal electrically coupled to a first word line. A second transistor has a first terminal electrically coupled to the second deep trench capacitor and a control terminal electrically coupled to a second word line. First and second bit lines are electrically coupled to the first and second transistors respectively. The first and second bit lines are separated and the first and second word lines are perpendicular to the bit line regions.
摘要翻译：一种用于检测DRAM器件中深沟槽电容器之间的电流泄漏的测试装置。测试装置设置在晶片的划线区域中。在测试装置中，第一沟槽电容器对具有并联连接的第一深沟槽电容器和第二深沟槽电容器。第一晶体管具有电耦合到第一深沟槽电容器的第一端子和电耦合到第一字线的控制端子。第二晶体管具有电耦合到第二深沟槽电容器的第一端子和电耦合到第二字线的控制端子。第一和第二位线分别电耦合到第一和第二晶体管。第一和第二位线被分离，第一和第二字线垂直于位线区域。

15. 发明授权

US07307849B2 Flash memory disk 失效
标题翻译：闪存盘
公开(公告)号：US07307849B2
公开(公告)日：2007-12-11
申请号：US11438429
申请日：2006-05-23
申请人： Lin-Ray Ho , Yu-Chang Lin
发明人： Lin-Ray Ho , Yu-Chang Lin
IPC分类号： H05K7/12
CPC分类号： H01R13/4538 , H05K5/0278
摘要： The frame of a flash memory disk has an opening, a resilient support and a pair of switches. The pair of switches is extended from the frame and is constricted at their connection portions. Two recesses are formed at inner surfaces of the pair of switches. A PCB includes a flash memory and a USB connector thereon. A carrier has a pair of resilient wing latches and a resilient end latch. The carrier accommodates the PCB and exposes the USB connector. The carrier slides within the frame to extend or to retract the USB connector through the opening. A spring is secured between the carrier and the frame. An upper housing is assembled upon the frame, wherein the upper housing includes a button contacting the resilient support. A lower housing is assembled to the frame.
摘要翻译：闪存盘的框架具有开口，弹性支撑件和一对开关。该对开关从框架延伸并在其连接部分处收缩。在一对开关的内表面形成两个凹槽。 PCB上包括闪存和USB连接器。载体具有一对弹性翼闩和弹性端闩。载体容纳PCB并暴露USB连接器。载体在框架内滑动以延伸或缩回USB连接器通过开口。弹簧固定在载体和框架之间。上壳体组装在框架上，其中上壳体包括接触弹性支撑件的按钮。下壳体组装到框架上。

16. 外观设计

USD547758S1 USB flash memory disk 有权
标题翻译： USB闪存盘
公开(公告)号：USD547758S1
公开(公告)日：2007-07-31
申请号：US29262657
申请日：2006-07-10
申请人： Lin-Ray Ho , Yu-Chang Lin
设计人： Lin-Ray Ho , Yu-Chang Lin

17. 发明申请

US20060150533A1 Double-layer fireproof curtain apparatus 审中-公开
标题翻译：双层防火幕设备
公开(公告)号：US20060150533A1
公开(公告)日：2006-07-13
申请号：US11250549
申请日：2005-10-17
申请人： Yu-Chang Lin , Eng-Nan Chuang
发明人： Yu-Chang Lin , Eng-Nan Chuang
IPC分类号： E04H6/00
CPC分类号： E06B9/40 , A62C2/10 , E06B9/68
摘要： A double-layer fireproof curtain apparatus includes a storing mechanism consisted of a frame and a first and a second activating units installed on both sides of the frame; two fireproof curtains installed separately on the first and second activating units, so that an air gap is formed when the two fireproof curtains are descended; at least one sensing unit electrically connected with the first and second activating units; and at least one control unit electrically connected with the first and second activating units. With the foregoing structure, the air gap can be used to achieve the effect of insulating heat, blocking fire, and resisting smoke in a fire accident, and comply with the regulation of fire control equipments.
摘要翻译：一种双层防火帘装置，包括由框架和安装在框架两侧的第一和第二启动单元组成的存放机构; 两个防火帘分别安装在第一和第二启动单元上，使得当两个防火帘下降时形成气隙; 至少一个感测单元，与所述第一和第二激活单元电连接; 以及与第一和第二激活单元电连接的至少一个控制单元。利用上述结构，可以利用气隙实现火灾事故中隔热，阻火，防烟的效果，符合消防设备的规定。

18. 发明申请

US20050269567A1 TEST KEY FOR MONITORING GATE CONDUCTOR TO DEEP TRENCH MISALIGNMENT 有权
标题翻译：用于监控门控导体深度偏差的测试键
公开(公告)号：US20050269567A1
公开(公告)日：2005-12-08
申请号：US10904652
申请日：2004-11-21
申请人： Yu-Chang Lin
发明人： Yu-Chang Lin
IPC分类号： H01L21/66 , H01L23/544
CPC分类号： H01L22/34 , Y10S257/905 , Y10S257/908
摘要： A test key for monitoring GC-DT misalignment is provided. Deep trench capacitors are embedded in an interlacing matrix manner. GC lines are defined on a substrate and passing over the deep trench capacitors. A first bit line contact pattern surrounded by first assistant bit line contact patterns is disposed on the right side of a first deep trench capacitor. A second bit line contact pattern surrounded by second assistant bit line contact patterns is disposed on the left side of a second deep trench capacitor. The test key has a mirror symmetric line. The first assistant bit line contact patterns and second assistant bit line contact patterns are symmetric with respect to the mirror symmetric line. An active area connects the first bit line contact pattern and the second bit line contact pattern. A signal-in bit line is connected to the first bit line contact and a signal-out bit line is connected to the second bit line contact. The rest rows of the bit lines are dummy bit lines and floating.
摘要翻译：提供了一个用于监测GC-DT不对准的测试键。深沟槽电容器以隔行矩阵的方式嵌入。 GC线定义在衬底上并穿过深沟槽电容器。由第一辅助位线接触图案包围的第一位线接触图案设置在第一深沟槽电容器的右侧。由第二辅助位线接触图案包围的第二位线接触图案设置在第二深沟槽电容器的左侧。测试键具有镜像对称线。第一辅助位线接触图案和第二辅助位线接触图案相对于镜像对称线对称。有源区域连接第一位线接触图案和第二位线接触图案。信号输入位线连接到第一位线触点，并且信号输出位线连接到第二位线触点。位线的其余行是虚拟位线和浮动。

19. 发明申请

US20050205942A1 METAL GATE WITH COMPOSITE FILM STACK 有权
标题翻译：金属门与复合膜片
公开(公告)号：US20050205942A1
公开(公告)日：2005-09-22
申请号：US10708708
申请日：2004-03-19
申请人： Shian-Jyh Lin , Chung-Yuan Lee , Yu-Chang LIN
发明人： Shian-Jyh Lin , Chung-Yuan Lee , Yu-Chang LIN
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/76 , H01L29/78 , H01L29/94 , H01L31/062
CPC分类号： H01L29/6656 , H01L21/28061 , H01L29/4941 , H01L29/78
摘要： A novel metal gate structure includes a gate oxide layer formed on a surface of a silicon substrate, a doped silicon layer stacked on the gate oxide layer, a CVD ultra-thin titanium nitride film deposited on the doped silicon layer, a tungsten nitride layer stacked on the CVD ultra-thin titanium nitride film, a tungsten layer stacked on the tungsten nitride layer, and a nitride cap layer stacked on the tungsten layer. A liquid phase deposition (LPD) oxide spacer is formed on each sidewall of the metal gate stack. A silicon nitride spacer is formed on the LPD oxide spacer. The thickness of the CVD ultra-thin titanium nitride film is between 10 and 100 angstroms.
摘要翻译：一种新颖的金属栅极结构，包括形成在硅衬底的表面上的栅极氧化层，堆叠在栅极氧化物层上的掺杂硅层，沉积在掺杂硅层上的CVD超薄氮化钛膜，堆叠的氮化钨层在CVD超薄氮化钛膜上堆叠在钨氮化物层上的钨层和层叠在钨层上的氮化物盖层。在金属栅极堆叠的每个侧壁上形成液相沉积（LPD）氧化物间隔物。在LPD氧化物间隔物上形成氮化硅间隔物。 CVD超薄氮化钛膜的厚度为10〜100埃。

20. 发明申请

US20050162215A1 Temperature sensing variable frequency generator 审中-公开
标题翻译：温度传感变频发生器
公开(公告)号：US20050162215A1
公开(公告)日：2005-07-28
申请号：US10761216
申请日：2004-01-22
申请人： Kuen-Huei Chang , Yu-Chang Lin , Chieng-Chung Chen
发明人： Kuen-Huei Chang , Yu-Chang Lin , Chieng-Chung Chen
IPC分类号： H03K3/354 , G05F3/02 , G11C11/406 , H03K3/0231 , H03K4/501 , H03K17/14
CPC分类号： H03K3/0231 , H03K4/501
摘要： A circuit for generating a current that comprises a first current generator providing a constant current in response to a constant voltage, a voltage generator providing a temperature dependent voltage, and a second current generator coupled to the voltage generator providing a variable current in response to the temperature dependent voltage.
摘要翻译：一种用于产生电流的电路，其包括响应于恒定电压提供恒定电流的第一电流发生器，提供与温度相关的电压的电压发生器，以及耦合到所述电压发生器的第二电流发生器，响应于所述电流发生器提供可变电流温度依赖电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式