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11. 发明授权

US07787320B2 Sense amplifier 有权
公开(公告)号：US07787320B2
公开(公告)日：2010-08-31
申请号：US12624103
申请日：2009-11-23
申请人： Yoshihiro Ueda , Yoshihisa Iwata , Toshiaki Edahiro , Toshihiro Suzuki
发明人： Yoshihiro Ueda , Yoshihisa Iwata , Toshiaki Edahiro , Toshihiro Suzuki
IPC分类号： G11C7/02
CPC分类号： G11C7/065 , G11C7/062 , G11C7/12 , G11C11/1673 , G11C16/0491 , G11C16/26 , G11C17/126 , G11C2207/002 , G11C2207/063
摘要： A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth FET is connected to a second input node, and its source is connected to the power source node. A sense operation is started by charging a first output node from the first input node with a first current and by charging a second output node from the second input node with a second current. The fifth and sixth FET are turned on after starting the sense operation.

12. 发明授权

US07623384B2 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US07623384B2
公开(公告)日：2009-11-24
申请号：US11767234
申请日：2007-06-22
申请人： Yoshihisa Iwata
发明人： Yoshihisa Iwata
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C8/10 , G11C16/0466 , G11C16/10 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/12
摘要： According to one embodiment, a nonvolatile semiconductor memory comprising: a source line side selection gate transistor that is having a first source region connected to a source line and a first gate electrode connected to a first select gate line; a bit line side selection gate transistor that is having a second drain region connected to a bit line and a second gate electrode connected to a second select gate line; a first memory cell string that is having a plurality of memory cell transistors connected in series, connected between a first drain region of the source line side selection gate transistor and a second source region of the bit line side selection gate transistor; and a second memory cell string that is having a plurality of memory cell transistors connected in series, connected in parallel with the first memory cell string; wherein the first memory cell string and the second memory cell string are stacked on a semiconductor substrate via an interlayer insulating film, wherein the source line side selection gate transistor and the bit line side selection gate transistor are placed on the semiconductor substrate.
摘要翻译：根据一个实施例，一种非易失性半导体存储器，包括：源极侧选择栅极晶体管，其具有连接到源极线的第一源极区域和与第一选择栅极线路连接的第一栅极电极; 位线侧选择栅极晶体管，其具有连接到位线的第二漏极区域和连接到第二选择栅极线路的第二栅极电极; 连接在源极侧选择栅极晶体管的第一漏极区域和位线侧选择栅极晶体管的第二源极区域之间的具有串联连接的多个存储单元晶体管的第一存储单元串; 以及第二存储单元串，其具有与第一存储单元串并联连接的串联连接的多个存储单元晶体管; 其中所述第一存储单元串和所述第二存储单元串经由层间绝缘膜堆叠在半导体衬底上，其中所述源极侧选择栅极晶体管和所述位线侧选择栅极晶体管被放置在所述半导体衬底上。

13. 发明授权

US07414880B2 Magnetoresistive effect element and magnetic memory 有权
标题翻译：磁阻效应元件和磁存储器
公开(公告)号：US07414880B2
公开(公告)日：2008-08-19
申请号：US11378358
申请日：2006-03-20
申请人： Tadashi Kai , Masahiko Nakayama , Sumio Ikegawa , Yoshiaki Fukuzumi , Yoshihisa Iwata
发明人： Tadashi Kai , Masahiko Nakayama , Sumio Ikegawa , Yoshiaki Fukuzumi , Yoshihisa Iwata
IPC分类号： G11C11/00
CPC分类号： H01L43/08 , G11C11/16 , H01L27/222
摘要： A magnetoresistive effect element includes a nonmagnetic layer having mutually facing first and second surfaces. A reference layer is provided on the first surface and has a fixed magnetization direction. A magnetization variable layer is provided on the second surface, has variable magnetization direction, and has a planer shape including a rectangular part, a first projected part, and a second projected part. The rectangular part has mutually facing first and second longer sides and mutually facing first and second shorter sides. The first projected part projects from the first longer side at a position shifted from the center toward the first shorter side. The second projected part projects from the second longer side at a position shifted from the center toward the second shorter side.
摘要翻译：磁阻效应元件包括具有相互面对的第一和第二表面的非磁性层。参考层设置在第一表面上并具有固定的磁化方向。磁化变化层设置在第二表面上，具有可变的磁化方向，并且具有包括矩形部分，第一突出部分和第二突出部分的平面形状。矩形部分具有相互面对的第一和第二长边以及相互面对的第一和第二短边。第一突出部从第一长边突出的位置从中心向第一短边移动。第二突出部从第二长边突出的位置从中心向第二短边移动。

14. 发明授权

US07375544B2 Semiconductor apparatus having logic level decision circuit and inter-semiconductor apparatus signal transmission system 失效
标题翻译：具有逻辑电平判定电路和半导体装置信号传输系统的半导体装置
公开(公告)号：US07375544B2
公开(公告)日：2008-05-20
申请号：US10623559
申请日：2003-07-22
申请人： Yoshihisa Iwata
发明人： Yoshihisa Iwata
IPC分类号： H03K19/003
CPC分类号： G11C11/16 , G11C7/062 , G11C7/14
摘要： In a signal transmission system between a plurality of semiconductor apparatuses, a logic level decision circuit deciding a logic level of an input signal in accordance with which of two reference signals a signal level of the input signal is close to, by using two reference signals Vref1, Vref0 having a “1” level and a “0” level as reference signals for deciding the logic level of the input signal having a binary logic level, is used as an input receiver of the each semiconductor apparatus.
摘要翻译：在多个半导体装置之间的信号传输系统中，逻辑电平判定电路通过使用两个参考信号Vref来决定输入信号的信号电平接近的两个参考信号中的哪一个的输入信号的逻辑电平在图1中，使用具有“1”电平和“0”电平的Vref 0作为用于确定具有二进制逻辑电平的输入信号的逻辑电平的参考信号作为每个半导体装置的输入接收器。

15. 发明授权

US07333359B2 Magnetic random access memory 失效
标题翻译：磁性随机存取存储器
公开(公告)号：US07333359B2
公开(公告)日：2008-02-19
申请号：US10419873
申请日：2003-04-22
申请人： Yoshiaki Asao , Yoshihisa Iwata , Yoshiaki Saito , Hiroaki Yoda , Tomomasa Ueda , Minoru Amano , Shigeki Takahashi , Tatsuya Kishi
发明人： Yoshiaki Asao , Yoshihisa Iwata , Yoshiaki Saito , Hiroaki Yoda , Tomomasa Ueda , Minoru Amano , Shigeki Takahashi , Tatsuya Kishi
IPC分类号： G11C11/00
CPC分类号： B82Y25/00 , G11C11/16 , H01F10/06 , H01F10/3254
摘要： A write word line is disposed right under a MTJ element. The write word line extends in an X direction, and side and lower surfaces of the write word line are coated with a hard magnetic material and yoke material. The hard magnetic material is magnetized by a surplus current passed through the write word line, and a characteristic of the MTJ element is corrected by residual magnetization. A data selection line (read/write bit line) is disposed right on the MTJ element. The data selection line extends in a Y direction intersecting with the X direction, and a part of the surface of the data selection line is coated with the yoke material.
摘要翻译：写字线被放置在MTJ元素的正下方。写字线在X方向上延伸，并且写字线的侧表面和下表面涂覆有硬磁材料和轭材料。硬磁材料被通过写入字线的剩余电流磁化，并且通过剩余磁化来校正MTJ元件的特性。数据选择线（读/写位线）设置在MTJ元件上。数据选择线在与X方向相交的Y方向上延伸，并且数据选择线的表面的一部分涂覆有轭材料。

16. 发明授权

US07326982B2 MRAM and method of manufacturing the same 有权
标题翻译： MRAM及其制造方法
公开(公告)号：US07326982B2
公开(公告)日：2008-02-05
申请号：US10933247
申请日：2004-09-03
申请人： Yoshihisa Iwata , Yoshiaki Fukuzumi , Tadashi Kai
发明人： Yoshihisa Iwata , Yoshiaki Fukuzumi , Tadashi Kai
IPC分类号： H01L27/108 , H01L29/94 , H01L31/119 , H01I29/76
CPC分类号： G11C11/16 , B82Y10/00 , H01L27/228 , H01L43/08 , H01L43/12
摘要： A magnetic memory device comprising, a magneto-resistance effect element that is provided at an intersection between a first write line and a second write line. And the magneto-resistance effect element having, an easy axis that extends in a direction of extension of the first write line, and a first conductive layer for electrical connection to the magneto-resistance effect element, the first conductive layer having sides which are in flush with sides of the magneto-resistance effect element.
摘要翻译：一种磁存储器件，包括：设置在第一写入线和第二写入线之间的交叉点处的磁阻效应元件。并且，所述磁阻效应元件具有沿所述第一写入线的延伸方向延伸的容易轴和用于与所述磁阻效应元件电连接的第一导电层，所述第一导电层具有位于与磁阻效应元件的两侧齐平。

17. 发明申请

US20070280021A1 SENSE AMPLIFIER 有权
标题翻译：感应放大器
公开(公告)号：US20070280021A1
公开(公告)日：2007-12-06
申请号：US11749412
申请日：2007-05-16
申请人： Yoshihiro Ueda , Yoshihisa Iwata , Toshiaki Edahiro , Toshihiro Suzuki
发明人： Yoshihiro Ueda , Yoshihisa Iwata , Toshiaki Edahiro , Toshihiro Suzuki
IPC分类号： G11C11/00 , G11C7/02
CPC分类号： G11C7/065 , G11C7/062 , G11C7/12 , G11C11/1673 , G11C16/0491 , G11C16/26 , G11C17/126 , G11C2207/002 , G11C2207/063
摘要： A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth FET is connected to a second input node, and its source is connected to the power source node. A sense operation is started by charging a first output node from the first input node with a first current and by charging a second output node from the second input node with a second current. The fifth and sixth FET are turned on after starting the sense operation.
摘要翻译：根据本发明的示例的读出放大器具有触发器连接的第一，第二，第三和第四FET。第五FET的漏极连接到第一输入节点，并且其源极连接到电源节点。第六FET的漏极连接到第二输入节点，其源极连接到电源节点。通过用第一电流从第一输入节点充电第一输出节点并且通过用第二电流从第二输入节点充电第二输出节点来开始感测操作。开始感测操作后，第五和第六FET导通。

18. 发明授权

US07239541B2 Spin-injection magnetic random access memory 有权
标题翻译：旋转注入磁性随机存取存储器
公开(公告)号：US07239541B2
公开(公告)日：2007-07-03
申请号：US11242906
申请日：2005-10-05
申请人： Yoshiaki Saito , Hideyuki Sugiyama , Tomoaki Inokuchi , Yoshihisa Iwata
发明人： Yoshiaki Saito , Hideyuki Sugiyama , Tomoaki Inokuchi , Yoshihisa Iwata
IPC分类号： G11C11/00 , G11C11/14
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/16 , H01L43/08
摘要： A spin-injection magnetic random access memory according to an embodiment of the invention includes a magnetoresistive element having a magnetic fixed layer whose magnetization direction is fixed, a magnetic recording layer whose magnetization direction can be changed by injecting spin-polarized electrons, and a tunnel barrier layer provided between the magnetic fixed layer and the magnetic recording layer, a bit line which passes spin-injection current through the magnetoresistive element, the spin-injection current being used for generation of the spin-polarized electrons, a writing word line through which assist current is passed, the assist current being used for the generation of an assist magnetic field in a magnetization easy-axis direction of the magnetoresistive element, and a driver/sinker which determines a direction of the spin-injection current and a direction of the assist current.
摘要翻译：根据本发明实施例的自旋注入磁随机存取存储器包括具有磁化方向固定的磁固定层的磁阻元件，其磁化方向可以通过注入自旋极化电子而改变的磁记录层，以及隧道设置在磁性固定层和磁记录层之间的阻挡层，使自旋注入电流通过磁阻元件的位线，用于产生自旋极化电子的自旋注入电流，写入字线，辅助电流通过，辅助电流用于在磁阻元件的易磁化易磁化方向上产生辅助磁场，以及确定自旋注入电流的方向和驱动器/ 协助电流

19. 发明申请

US20060198224A1 Magnetic memory device 失效
标题翻译：磁存储器件
公开(公告)号：US20060198224A1
公开(公告)日：2006-09-07
申请号：US11133383
申请日：2005-05-20
申请人： Yoshihiro Ueda , Yoshihisa Iwata
发明人： Yoshihiro Ueda , Yoshihisa Iwata
IPC分类号： G11C7/02
CPC分类号： G11C11/16
摘要： A magnetic memory device includes a plurality of variable resistance elements arranged in parallel between a first and second nodes and having resistance values which vary depending on data stored in the elements, a selection transistor connected to the first node to perform selection on the plurality of variable resistance elements, and a bit line connected to the second node. A plurality of current paths including the variable resistance elements between the first and second nodes have different resistance values.
摘要翻译：一种磁存储器件包括多个可变电阻元件，它们并联布置在第一和第二节点之间，并具有根据存储在元件中的数据而变化的电阻值;连接到第一节点的选择晶体管，以对多个变量进行选择电阻元件和连接到第二节点的位线。包括第一和第二节点之间的可变电阻元件的多个电流路径具有不同的电阻值。

20. 发明授权

US07102945B2 Read circuit of semiconductor and read method using a self-reference sensing technique 失效
标题翻译：使用自参考感测技术的半导体读取电路和读取方法
公开(公告)号：US07102945B2
公开(公告)日：2006-09-05
申请号：US11014862
申请日：2004-12-20
申请人： Kenji Tsuchida , Junichi Miyamoto , Yoshihisa Iwata
发明人： Kenji Tsuchida , Junichi Miyamoto , Yoshihisa Iwata
IPC分类号： G11C7/00
CPC分类号： G11C11/16 , G11C7/06 , G11C7/1051 , G11C7/1069 , G11C7/12 , G11C11/1673 , G11C2207/005
摘要： A read circuit of a semiconductor memory according to the present invention is based on a self-reference sensing technique by which data stored in a memory cell is determined by first and second signals read out from a memory cell through first and second read operations. This read circuit includes a sense amplifier which determines the data stored in the memory cell based on a potential of an input node, a transfer transistor which is connected between the memory cell and the input node, a precharge circuit which sets the input node to a precharge potential, and a VBIAS generator which turns the transfer transistor cutoff based on the first signal.
摘要翻译：根据本发明的半导体存储器的读取电路基于自参考感测技术，通过第一和第二读取操作从存储器单元读出的第一和第二信号确定存储单元中存储的数据。该读取电路包括读出放大器，其基于输入节点的电位确定存储在存储器单元中的数据，连接在存储单元和输入节点之间的传输晶体管，将输入节点设置为预充电电位，以及基于第一信号使转移晶体管截止的VBIAS发生器。

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