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11. 发明授权

US07503026B2 Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit 有权
标题翻译：细胞，标准细胞，标准细胞库，使用标准细胞的放置方法和半导体集成电路
公开(公告)号：US07503026B2
公开(公告)日：2009-03-10
申请号：US11305191
申请日：2005-12-19
申请人： Miwa Ichiryu , Toshiyuki Moriwaki , Tetsurou Toubou
发明人： Miwa Ichiryu , Toshiyuki Moriwaki , Tetsurou Toubou
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , H01L27/11807
摘要： A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to “a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area.
摘要翻译：根据本发明的单元包括能够传输输入信号或输出信号并在设计半导体集成电路中作为最小单位的多个端子，其中多个端子位于沿Y方向排列的布线栅格上其是与用于自动布置和布线的电池的电源布线垂直的方向，并且具有在与电源布线并联的方向的X方向上延伸的形状，更具体地说，例如，终端的长边尺寸等于“X方向上的路由网格间隔+布线宽度”，根据该结构，小区面积减小，有利于芯片面积的减少。

12. 发明申请

US20080265494A1 Sheet Material Accumulating Method And Sheet Material Accumulating Apparatus 审中-公开
标题翻译：板材积累方法和片材积累装置
公开(公告)号：US20080265494A1
公开(公告)日：2008-10-30
申请号：US11918863
申请日：2006-04-27
申请人： Toshiyuki Moriwaki , Kenji Mishima , Haruhiro Otsuka , Hitoshi Katsuragawa
发明人： Toshiyuki Moriwaki , Kenji Mishima , Haruhiro Otsuka , Hitoshi Katsuragawa
IPC分类号： B65H31/06
CPC分类号： B65H31/06 , B65H2301/42146 , B65H2301/4223 , B65H2513/40 , B65H2515/34 , B65H2220/02 , B65H2220/01
摘要： Provided are a sheet material accumulating method and a sheet material accumulating apparatus capable of performing a proper accumulation of a sheet material that does not produce a defective in the next process even when an overlap condition of a conveyed sheet material, such as a printed sheet, varies.Provided is a sheet material accumulating method for accumulating the sheet material W continuously conveyed from the above while a part of the sheet material W is overlapped, with the sheet material standing on a lower horizontal table 7, including the steps of: detecting a backpressure F that a bundle of sheet materials applied to a holder 8 for preventing a head side collapse of a bundle of sheet materials accumulated on the table during an accumulation process; and controlling a movement of the holder in an accumulation direction so that a backpressure may maintain a predetermined magnitude.
摘要翻译：提供一种片材积累方法和片材积累装置，即使在输送的片材（例如印刷片材）的重叠状态下，也能够在下一个处理中进行不产生缺陷的片材的适当堆积，不一样提供一种片材积累方法，用于在片材W的一部分重叠的同时将片材材料W从上述连续传送，并将片材材料放置在下水平台7上，包括以下步骤：检测背压F 将一束片材施加到保持器8上，用于防止在积聚过程中堆积在桌子上的一束片材的头侧塌陷; 并且控制保持器在累积方向上的移动，使得背压可以保持预定的大小。

13. 发明授权

US06490715B1 Cell library database and design aiding system 有权
标题翻译：细胞库数据库和设计辅助系统
公开(公告)号：US06490715B1
公开(公告)日：2002-12-03
申请号：US09550352
申请日：2000-04-14
申请人： Toshiyuki Moriwaki , Shiro Sakiyama , Hiroo Yamamoto , Jun Kajiwara , Masayoshi Kinoshita
发明人： Toshiyuki Moriwaki , Shiro Sakiyama , Hiroo Yamamoto , Jun Kajiwara , Masayoshi Kinoshita
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A cell library database includes function information of standard cells which are basic circuits forming a logical device, each of the standard cell comprising at least one of power supply terminal as logical terminals, the function information of the standard cell containing logical information or delay information of the power supply terminal relative to an output terminal, or function information of macro cells which are functional circuits forming a logical device, each of the macro cell comprising at least one of power supply terminals as logical terminals, the function information of the macro cell containing logical information or delay information of said power supply terminals relative to an output terminal. A design aiding system uses the cell library database to execute logical simulation, etc.
摘要翻译：单元库数据库包括作为形成逻辑装置的基本电路的标准单元的功能信息，标准单元中的每一个包括作为逻辑端的电源端子中的至少一个，包含逻辑信息或延迟信息的标准单元的功能信息所述电源端子相对于输出端子，或作为形成逻辑装置的功能电路的宏电池的功能信息，所述宏电池单元包括作为逻辑端子的电源端子中的至少一个，所述宏单元的功能信息包含所述电源端子相对于输出端子的逻辑信息或延迟信息。设计辅助系统使用单元库数据库执行逻辑仿真等。

14. 发明授权

US07597318B2 Sheet material accumulating apparatus 有权
公开(公告)号：US07597318B2
公开(公告)日：2009-10-06
申请号：US11921939
申请日：2006-05-23
申请人： Toshiyuki Moriwaki , Kenji Mishima , Haruhiro Otsuka , Hitoshi Katsuragawa
发明人： Toshiyuki Moriwaki , Kenji Mishima , Haruhiro Otsuka , Hitoshi Katsuragawa
IPC分类号： B65H29/00
CPC分类号： B65H31/06 , B65H15/00 , B65H29/66 , B65H2301/33212 , B65H2301/3423 , B65H2301/42146 , B65H2402/10 , B65H2402/351 , B65H2404/2611 , B65H2511/15 , B65H2701/1912
摘要： A sheet material accumulating apparatus for accumulating a sheet material W into an accumulated bundle P by arranging it in a mutually overlapping state is configured to be able to suppress an enlargement, a higher tallness, more complication, etc. of the apparatus and attain a curtailment of various costs, including a manufacture cost.The apparatus has a primary conveyer 2, a second conveyer 3, and an accumulation unit 4, the accumulation unit 4 has a posture conversion unit 35 for converting the sheet material W in a flatted posture into that in a standing posture, a descend conveyer unit 36 for conveying the sheet material W downward while keeping the standing posture, and a table top 7 for accumulating the received sheet material W sequentially while supporting it in a standup posture; the primary conveyer 2 has a flat conveyance plane 6 at a substantially same height as the table top 7; and the secondary conveyer 3 twists the sheet material W along a conveyance direction so that top and bottom thereof may be inverted while it is conveyed in a rise inclined direction.

15. 发明申请

US20080246091A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20080246091A1
公开(公告)日：2008-10-09
申请号：US12061947
申请日：2008-04-03
申请人： Hideaki Kondo , Toshiyuki Moriwaki , Masaki Tamaru , Takashi Andoh
发明人： Hideaki Kondo , Toshiyuki Moriwaki , Masaki Tamaru , Takashi Andoh
IPC分类号： H01L27/08
CPC分类号： H01L27/0207 , H01L27/11807
摘要： A semiconductor integrated circuit device capable of suppressing variations in transistor characteristics due to the well proximity effect is provided. Standard cell rows are arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction. In the standard cell rows, positions of the N well and the P region in the vertical direction are switched every other row. Adjacent standard cell rows share the P region or the N well. A distance from a PMOS transistor located at an end of a standard cell row to an end of an N well is greater than or equal to a width of an N well shared by standard cell rows.
摘要翻译：提供能够抑制由于良好邻近效应引起的晶体管特性变化的半导体集成电路器件。标准单元行排列成垂直方向，每个标准单元行包括沿水平方向布置的标准单元。在标准单元行中，N阱和P区域在垂直方向上的位置每隔一行被切换。相邻的标准单元行共享P区或N阱。位于标准单元行的端部到N阱的端部的PMOS晶体管的距离大于或等于标准单元行共享的N阱的宽度。

16. 发明授权

US07369618B2 Signal transmission circuit 失效
标题翻译：信号传输电路
公开(公告)号：US07369618B2
公开(公告)日：2008-05-06
申请号：US11132206
申请日：2005-05-19
申请人： Keiichi Kusumoto , Toshiyuki Moriwaki , Tsuguyasu Hatsuda , Tetsurou Toubou
发明人： Keiichi Kusumoto , Toshiyuki Moriwaki , Tsuguyasu Hatsuda , Tetsurou Toubou
IPC分类号： H04B3/00
CPC分类号： H04L25/028 , H04L25/0292 , H04L25/03878
摘要： A signal is transmitted in synchronization with a clock signal that repeats H and L levels indicating a preparation period and a transmission period, respectively. A transmitting circuit includes a transmitting capacitor, an input switch for setting a voltage in accordance with an input digital signal in the transmitting capacitor at preparation period, and a transmitting switch for generating a small voltage change in the signal line at transmission period, the voltage change being in accordance with a voltage of the transmitting capacitor. A receiving circuit includes an inverter with a CMOS configuration, a receiving capacitor inserted between an input terminal and an output terminal of the inverter, an equalizing switch for short-circuiting the input terminal and the output terminal of the inverter so as to set the voltage of the signal line to a predetermined voltage at preparation period, and a latch for supplying an output digital signal by performing logic amplification of the voltage of the output terminal of the inverter for each transmission period, and for holding the output for each preparation period.
摘要翻译：与重复分别表示准备期间和发送期间的H，L电平的时钟信号同步地发送信号。发送电路包括发送电容器，用于在准备期间根据发送电容器中的输入数字信号设定电压的输入开关和用于在发送期间产生信号线中的小电压变化的发送开关，根据发送电容器的电压进行变化。接收电路包括具有CMOS配置的反相器，插入在反相器的输入端子和输出端子之间的接收电容器，用于使逆变器的输入端子和输出端子短路的均衡开关，以便设置电压的信号线在预备期间达到预定电压，以及锁存器，用于通过在每个传输周期内执行对逆变器的输出端子的电压的逻辑放大来提供输出数字信号，并且用于保持每个准备周期的输出。

17. 发明申请

US20060017087A1 Semiconductor device and method of manufacturing the same utilizing permittivity of an insulating layer to provide a desired cross conductive layer capacitance property 审中-公开
标题翻译：半导体器件及其制造方法利用绝缘层的介电常数提供期望的交叉导电层电容性能
公开(公告)号：US20060017087A1
公开(公告)日：2006-01-26
申请号：US11220058
申请日：2005-09-06
申请人： Masaki Tamaru , Toshiyuki Moriwaki , Ryoichi Suzuki
发明人： Masaki Tamaru , Toshiyuki Moriwaki , Ryoichi Suzuki
IPC分类号： H01L29/94
CPC分类号： H01L21/76897 , H01L21/76829 , H01L21/76834 , H01L23/5223 , H01L23/5286 , H01L28/40 , H01L28/82 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： A supplemental capacitor is formed using the large capacitance between the wirings (M11 and M12) and that between the through-holes (B11 and B12) because of downsizing of the process technique. The inter-wiring capacitor and inter-through-hole capacitor can be arranged at any optional position within the semiconductor device. The supplemental capacitor can be easily formed in the vicinity of the area where switching noise is generated, thereby effectively realizing the countermeasure for power source noise. In the process technique with advanced downsizing, a capacitor having large capacitance can be formed with a smaller area. In addition, the capacitor can be formed in the same process as the other device such as a transistor without adding any special step.
摘要翻译：由于处理技术的小型化，使用布线（M 11和M 12）之间的大电容以及通孔（B 11和B 12）之间的大电容形成补充电容器。布线电容器和通孔间电容器可以布置在半导体器件内的任何可选位置。补充电容器可以容易地形成在产生开关噪声的区域附近，从而有效地实现了电源噪声的对策。在具有先进的小型化的工艺技术中，可以形成具有较小电容的电容器，其面积较小。此外，电容器可以以与其他器件（例如晶体管）相同的工艺形成，而不增加任何特殊的步骤。

18. 发明申请

US20050207504A1 Signal transmission circuit 失效
公开(公告)号：US20050207504A1
公开(公告)日：2005-09-22
申请号：US11132206
申请日：2005-05-19
申请人： Keiichi Kusumoto , Toshiyuki Moriwaki , Tsuguyasu Hatsuda , Tetsurou Toubou
发明人： Keiichi Kusumoto , Toshiyuki Moriwaki , Tsuguyasu Hatsuda , Tetsurou Toubou
IPC分类号： H03K19/096 , H03K17/04 , H03K19/0175 , H04L25/02 , H04L25/03 , H04L25/00
CPC分类号： H04L25/028 , H04L25/0292 , H04L25/03878
摘要： A signal is transmitted in synchronization with a clock signal that repeats H and L levels indicating a preparation period and a transmission period, respectively. A transmitting circuit includes a transmitting capacitor, an input switch for setting a voltage in accordance with an input digital signal in the transmitting capacitor at preparation period, and a transmitting switch for generating a small voltage change in the signal line at transmission period, the voltage change being in accordance with a voltage of the transmitting capacitor. A receiving circuit includes an inverter with a CMOS configuration, a receiving capacitor inserted between an input terminal and an output terminal of the inverter, an equalizing switch for short-circuiting the input terminal and the output terminal of the inverter so as to set the voltage of the signal line to a predetermined voltage at preparation period, and a latch for supplying an output digital signal by performing logic amplification of the voltage of the output terminal of the inverter for each transmission period, and for holding the output for each preparation period.

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