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11. 发明授权

US07550347B2 Methods of forming integrated circuit device gate structures 有权
标题翻译：形成集成电路器件门结构的方法
公开(公告)号：US07550347B2
公开(公告)日：2009-06-23
申请号：US11510059
申请日：2006-08-25
申请人： Sam-jong Choi , Yong-kwon Kim , Kyoo-chul Cho , Kyung-soo Kim , Jae-ryong Jung , Tae-soo Kang , Sang-Sig Kim
发明人： Sam-jong Choi , Yong-kwon Kim , Kyoo-chul Cho , Kyung-soo Kim , Jae-ryong Jung , Tae-soo Kang , Sang-Sig Kim
IPC分类号： H01L21/00
CPC分类号： H01L21/28282 , B82Y10/00 , H01L29/42324 , H01L29/42332 , H01L29/792 , H01L29/7923
摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.
摘要翻译：形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。将元素周期表第4组的选定元素的离子注入到第一电介质层中，以在第一电介质层中形成具有小于约0.5厘米每秒（cm 2 / s）的热扩散率的离子，从而在第一电介质层中形成电荷存储区，在电荷存储区域下的隧道介电层。金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。还提供用于集成电路器件和存储单元的栅极结构。

12. 发明申请

US20070128846A1 Integrated circuit device gate structures and methods of forming the same 有权
标题翻译：集成电路器件栅极结构及其形成方法
公开(公告)号：US20070128846A1
公开(公告)日：2007-06-07
申请号：US11510059
申请日：2006-08-25
申请人： Sam-jong Choi , Yong-kwon Kim , Kyoo-chul Cho , Kyung-soo Kim , Jae-ryong Jung , Tae-soo Kang , Sang-Sig Kim
发明人： Sam-jong Choi , Yong-kwon Kim , Kyoo-chul Cho , Kyung-soo Kim , Jae-ryong Jung , Tae-soo Kang , Sang-Sig Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/28282 , B82Y10/00 , H01L29/42324 , H01L29/42332 , H01L29/792 , H01L29/7923
摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.
摘要翻译：形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。将元素周期表第4组的选定元素的离子注入到第一介电层中，并且具有小于约0.5厘米每秒（cm 2 / s）的热扩散率，从而形成电荷存储区域，在电荷存储区域下方具有隧道介电层。金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。还提供用于集成电路器件和存储单元的栅极结构。

13. 发明申请

US20070034950A1 SEMICONDUCTOR WAFER AND METHOD OF FABRICATING THE SAME 有权
标题翻译： SEMICONDUCTOR WAFER AND METHOD OF FABRISTING THE SAME
公开(公告)号：US20070034950A1
公开(公告)日：2007-02-15
申请号：US11463137
申请日：2006-08-08
申请人： Young-Soo PARK , Kyoo-Chul CHO , Shin-Hyeok HAN , Tae-Soo KANG
发明人： Young-Soo PARK , Kyoo-Chul CHO , Shin-Hyeok HAN , Tae-Soo KANG
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/045 , H01L21/76251 , H01L21/84 , H01L27/1203 , H01L29/78687 , H01L29/78696
摘要： Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second crystallographic orientation. The performance of a semiconductor device with unit elements that use charges, which are activated in high mobility to the crystallographic orientation, as carriers is enhanced. The semiconductor wafer is completed by forming the semiconductor layer with the second crystallographic orientation on the plane of the first crystallographic orientation, growing an epitaxial layer, forming the insulation layer on the epitaxial layer, and then bonding the insulation layer to the base substrate.
摘要翻译：公开了半导体晶片及其制造方法。半导体晶片由在基底基板上的绝缘层上形成的半导体层构成。半导体层包括以第一晶体取向组织的表面区域和以第二晶体取向组织的另一表面区域。带有单元元件的半导体器件的性能随着载流子的增强而被使用以高结晶取向的高迁移率激活的电荷。半导体晶片通过在第一晶体取向的平面上形成具有第二晶体取向的半导体层，生长外延层，在外延层上形成绝缘层，然后将绝缘层接合到基底来完成。

14. 外观设计

USD329850S Portable cassette tape recorder 失效
公开(公告)号：USD329850S
公开(公告)日：1992-09-29
申请号：US473700
申请日：1990-02-02
申请人： Tae Soo Kang
设计人： Tae Soo Kang

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