专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20100255674A1 METHOD OF FORMING CONTACT STRUCTURE 有权
标题翻译：形成接触结构的方法
公开(公告)号：US20100255674A1
公开(公告)日：2010-10-07
申请号：US12750157
申请日：2010-03-30
申请人： Kyung-Rae BYUN , Suk-Ho Joo , Min-Joon Park
发明人： Kyung-Rae BYUN , Suk-Ho Joo , Min-Joon Park
IPC分类号： H01L21/768
CPC分类号： H01L21/76879 , H01L21/76823 , H01L21/76843 , H01L21/76867 , H01L21/76876 , H01L2221/1094 , Y10S977/742 , Y10S977/936
摘要： Provided is a method of forming a contact structure. The method includes forming a conductive pattern on a substrate. An interlayer insulating layer covering the conductive pattern is formed. The interlayer insulating layer is patterned to form an opening partially exposing the conductive pattern. An oxide layer is formed on substantially the entire surface of the substrate on which the opening is formed. A reduction process is performed to reduce the oxide layer. Here, the oxide layer on a bottom region of the opening is reduced to a catalyst layer, and the oxide layer on a region other than the bottom region of the opening is reduced to a non-catalyst layer. A nano material is grown from the catalyst layer, so that a contact plug is formed in the opening.
摘要翻译：提供一种形成接触结构的方法。该方法包括在衬底上形成导电图案。形成覆盖导电图案的层间绝缘层。图案化层间绝缘层以形成部分地暴露导电图案的开口。在其上形成有开口的基板的整个表面上形成氧化物层。进行还原处理以减少氧化物层。这里，开口底部的氧化物层被还原为催化剂层，除开口底部以外的区域的氧化物层还原为非催化剂层。从催化剂层生长纳米材料，使得在开口中形成接触塞。

12. 发明授权

US07494866B2 Semiconductor device and related method of manufacture 有权
标题翻译：半导体器件及相关制造方法
公开(公告)号：US07494866B2
公开(公告)日：2009-02-24
申请号：US11403901
申请日：2006-04-14
申请人： Hwa-Young Ko , Kyung-Rae Byun , Hyoung-Seub Rhie , Hee-Seok Kim , Jin-Hwan Ham , Suk-Ho Joo
发明人： Hwa-Young Ko , Kyung-Rae Byun , Hyoung-Seub Rhie , Hee-Seok Kim , Jin-Hwan Ham , Suk-Ho Joo
IPC分类号： H01L21/8242
CPC分类号： H01L23/485 , H01L27/105 , H01L27/11502 , H01L27/11507 , H01L27/11509 , H01L28/55 , H01L28/65 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are a semiconductor device and a related method of manufacture. The semiconductor device comprises a semiconductor substrate, a conductive structure including contact regions and gate structures formed on the semiconductor substrate, a protection layer formed on the gate structures, an insulation layer formed on the protection layer, and a plurality of contacts directly contacting the contact regions and the semiconductor substrate through the insulation layer, wherein the contacts have substantially different heights from each other.
摘要翻译：公开了半导体器件和相关的制造方法。半导体器件包括半导体衬底，包括形成在半导体衬底上的接触区域和栅极结构的导电结构，形成在栅极结构上的保护层，形成在保护层上的绝缘层，以及直接接触触点的多个触点区域和半导体衬底通过绝缘层，其中触点彼此具有实质上不同的高度。

13. 发明申请

US20080272357A1 Phase Changeable Memory Device Structures 有权
标题翻译：相变存储器件结构
公开(公告)号：US20080272357A1
公开(公告)日：2008-11-06
申请号：US12132920
申请日：2008-06-04
申请人： Hideki Horii , Suk-Ho Joo , Ji-Hye Yi
发明人： Hideki Horii , Suk-Ho Joo , Ji-Hye Yi
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/143 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.
摘要翻译：可相变存储器件可以包括衬底，衬底上的绝缘层，第一和第二电极以及第一和第二电极之间的相变材料的图案。更具体地，绝缘层可以在其中具有孔，并且第一电极可以在绝缘层中的孔中。此外，第二电极的部分可以延伸超过相变材料图案的边缘。还讨论了相关方法。

14. 发明申请

US20060237851A1 Semiconductor device and related method of manufacture 有权
公开(公告)号：US20060237851A1
公开(公告)日：2006-10-26
申请号：US11403901
申请日：2006-04-14
申请人： Hwa-Young Ko , Kyung-Rae Byun , Hyoung-Seub Rhie , Hee-Seok Kim , Jin-Hwan Ham , Suk-Ho Joo
发明人： Hwa-Young Ko , Kyung-Rae Byun , Hyoung-Seub Rhie , Hee-Seok Kim , Jin-Hwan Ham , Suk-Ho Joo
IPC分类号： H01L23/52
CPC分类号： H01L23/485 , H01L27/105 , H01L27/11502 , H01L27/11507 , H01L27/11509 , H01L28/55 , H01L28/65 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are a semiconductor device and a related method of manufacture. The semiconductor device comprises a semiconductor substrate, a conductive structure including contact regions and gate structures formed on the semiconductor substrate, a protection layer formed on the gate structures, an insulation layer formed on the protection layer, and a plurality of contacts directly contacting the contact regions and the semiconductor substrate through the insulation layer, wherein the contacts have substantially different heights from each other.

15. 发明授权

US06887720B2 Ferroelectric memory device and method of forming the same 失效
标题翻译：铁电存储器件及其形成方法
公开(公告)号：US06887720B2
公开(公告)日：2005-05-03
申请号：US10756443
申请日：2004-01-12
申请人： Suk-Ho Joo
发明人： Suk-Ho Joo
IPC分类号： H01L27/105 , H01L21/02 , H01L21/3213 , H01L21/8242 , H01L21/8246 , H01L27/02 , H01L21/00
CPC分类号： H01L28/60 , H01L21/32136 , H01L21/32139 , H01L27/0207 , H01L27/10852 , H01L27/10882
摘要： The present invention discloses a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes a semiconductor substrate, a capacitor lower electrode, a ferroelectric layer, and a capacitor upper electrode. The semiconductor substrate has a lower structure. The capacitor lower electrode has a cylindrical shape and a certain height. The ferroelectric layer is conformally stacked over substantially the entire surface of the semiconductor substrate including the capacitor lower electrode. The capacitor upper electrode has a spacer shape and is formed around the sidewall of the ferroelectric layer that surrounds the lower electrode. In the method of forming the ferroelectric memory device, a semiconductor substrate having an interlayer dielectric layer and a lower electrode contact formed through the interlayer dielectric layer is prepared. A cylindrical capacitor lower electrode is formed on the interlayer dielectric layer to cover the contact. A ferroelectric layer is conformally stacked at the semiconductor substrate having the capacitor lower electrode. A spacer-shaped upper electrode is formed around the sidewall of the ferroelectric layer that surrounds the capacitor lower electrode.
摘要翻译：本发明公开了一种铁电存储器件及其形成方法。铁电存储器件包括半导体衬底，电容器下电极，铁电层和电容器上电极。半导体衬底具有较低的结构。电容器下电极具有圆筒形状和一定高度。铁电层在包括电容器下电极的半导体衬底的整个表面的整个表面上共形堆叠。电容器上电极具有间隔件形状，并且围绕下电极的铁电层的侧壁形成。在形成强电介质存储器件的方法中，制备具有通过层间介质层形成的层间绝缘层和下电极接触的半导体衬底。在层间电介质层上形成圆柱形电容器下电极以覆盖触点。在具有电容器下电极的半导体衬底上共形层叠铁电层。在围绕电容器下电极的铁电体层的侧壁周围形成间隔物状的上部电极。

16. 发明授权

US06717196B2 Ferroelectric memory device 失效
标题翻译：铁电存储器件
公开(公告)号：US06717196B2
公开(公告)日：2004-04-06
申请号：US10232928
申请日：2002-08-30
申请人： Suk-Ho Joo
发明人： Suk-Ho Joo
IPC分类号： H01L2976
CPC分类号： H01L28/60 , H01L21/32136 , H01L21/32139 , H01L27/0207 , H01L27/10852 , H01L27/10882
摘要： The present invention discloses a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes a semiconductor substrate, a capacitor lower electrode, a ferroelectric layer, and a capacitor upper electrode. The semiconductor substrate has a lower structure. The capacitor lower electrode has a cylindrical shape and a certain height. The ferroelectric layer is conformally stacked over substantially the entire surface of the semiconductor substrate including the capacitor lower electrode. The capacitor upper electrode has a spacer shape and is formed around the sidewall of the ferroelectric layer that surrounds the lower electrode. In the method of forming the ferroelectric memory device, a semiconductor substrate having an interlayer dielectric layer and a lower electrode contact formed through the interlayer dielectric layer is prepared. A cylindrical capacitor lower electrode is formed on the interlayer dielectric layer to cover the contact. A ferroelectric layer is conformally stacked at the semiconductor substrate having the capacitor lower electrode. A spacer-shaped upper electrode is formed around the sidewall of the ferroelectric layer that surrounds the capacitor lower electrode.
摘要翻译：本发明公开了一种铁电存储器件及其形成方法。铁电存储器件包括半导体衬底，电容器下电极，铁电层和电容器上电极。半导体衬底具有较低的结构。电容器下电极具有圆筒形状和一定高度。铁电层在包括电容器下电极的半导体衬底的整个表面的整个表面上共形堆叠。电容器上电极具有间隔件形状，并且围绕下电极的铁电层的侧壁形成。在形成强电介质存储器件的方法中，制备具有通过层间介质层形成的层间绝缘层和下电极接触的半导体衬底。在层间电介质层上形成圆柱形电容器下电极以覆盖触点。在具有电容器下电极的半导体基板上共形层叠铁电体层。在围绕电容器下电极的铁电体层的侧壁周围形成间隔物状的上部电极。

17. 发明授权

US07763878B2 Phase changeable memory device structures 有权
标题翻译：相变存储器件结构
公开(公告)号：US07763878B2
公开(公告)日：2010-07-27
申请号：US12132920
申请日：2008-06-04
申请人： Hideki Horii , Suk-Ho Joo , Ji-Hye Yi
发明人： Hideki Horii , Suk-Ho Joo , Ji-Hye Yi
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/143 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.
摘要翻译：可相变存储器件可以包括衬底，衬底上的绝缘层，第一和第二电极以及第一和第二电极之间的相变材料的图案。更具体地，绝缘层可以在其中具有孔，并且第一电极可以在绝缘层中的孔中。此外，第二电极的部分可以延伸超过相变材料图案的边缘。还讨论了相关方法。

18. 发明申请

US20060273366A1 Methods of manufacturing ferroelectric capacitors and semiconductor devices 审中-公开
标题翻译：制造铁电电容器和半导体器件的方法
公开(公告)号：US20060273366A1
公开(公告)日：2006-12-07
申请号：US11447545
申请日：2006-06-06
申请人： Hwa-Young Ko , Suk-Ho Joo , Byoung-Jae Bae , Hee-Seok Kim , Kyung-Rae Byun , Jin-Hwan Ham
发明人： Hwa-Young Ko , Suk-Ho Joo , Byoung-Jae Bae , Hee-Seok Kim , Kyung-Rae Byun , Jin-Hwan Ham
IPC分类号： H01L29/94
CPC分类号： H01L28/55 , H01L21/32139 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： In a method of manufacturing a ferroelectric capacitor, a lower electrode layer is formed on a substrate. The lower electrode layer includes at least one lower electrode film. A ferroelectric layer is formed on the lower electrode layer, and then an upper electrode layer is formed on the ferroelectric layer. A hard mask structure is formed on the upper electrode layer. The hard mask structure includes a first hard mask and a second hard mask. An upper electrode, a ferroelectric layer pattern and a lower electrode are formed by partially etching the upper electrode layer, the ferroelectric layer and the lower electrode layer using the hard mask structure. The hard mask structure may prevent damage to the ferroelectric layer and may enlarge an effective area of the ferroelectric capacitor so that the ferroelectric capacitor may have enhanced electrical and ferroelectric characteristics.
摘要翻译：在制造铁电电容器的方法中，在基板上形成下电极层。下电极层包括至少一个下电极膜。在下电极层上形成铁电体层，在铁电层上形成上电极层。在上电极层上形成硬掩模结构。硬掩模结构包括第一硬掩模和第二硬掩模。通过使用硬掩模结构部分蚀刻上电极层，铁电层和下电极层，形成上电极，铁电层图案和下电极。硬掩模结构可以防止对铁电层的损坏，并且可以增加铁电电容器的有效面积，使得铁电电容器可以具有增强的电和铁电特性。

19. 发明申请

US20060148125A1 Phase changable memory device structures 有权
标题翻译：相变存储器件结构
公开(公告)号：US20060148125A1
公开(公告)日：2006-07-06
申请号：US11364950
申请日：2006-03-01
申请人： Hideki Horii , Suk-ho Joo , Ji-Hye Yi
发明人： Hideki Horii , Suk-ho Joo , Ji-Hye Yi
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/143 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.
摘要翻译：可相变存储器件可以包括衬底，衬底上的绝缘层，第一和第二电极以及第一和第二电极之间的相变材料的图案。更具体地，绝缘层可以在其中具有孔，并且第一电极可以在绝缘层中的孔中。此外，第二电极的部分可以延伸超过相变材料图案的边缘。还讨论了相关方法。

20. 发明授权

US5795817A MOS transistor adopting titanium-carbon-nitride gate electrode and manufacturing method thereof 失效
标题翻译：采用氮化钛栅电极的MOS晶体管及其制造方法
公开(公告)号：US5795817A
公开(公告)日：1998-08-18
申请号：US619361
申请日：1996-03-21
申请人： Suk-ho Joo , Choong-ryul Paik , Ki-hong Lee
发明人： Suk-ho Joo , Choong-ryul Paik , Ki-hong Lee
IPC分类号： H01L21/28 , H01L29/49 , H01L29/78
CPC分类号： H01L21/28088 , H01L29/4966
摘要： A MOS transistor employing a titanium-carbon-nitride (TiCN) gate electrode is provided. The MOS transistor has a gate insulating film, a gate electrode, and a source/drain region on a semiconductor substrate. The gate electrode is formed of a single TiCN film or a double film having a TiCN film and a low-resistant metal film formed thereon. The TiCN gate electrode exhibits a low resistance of about 80-100 .mu..OMEGA.-cm and can control variations in Fermi energy level.
摘要翻译：提供采用钛 - 氮化钛（TiCN）栅电极的MOS晶体管。 MOS晶体管在半导体衬底上具有栅极绝缘膜，栅极电极和源极/漏极区域。栅极由单个TiCN膜或其上形成有TiCN膜和低电阻金属膜的双层膜形成。 TiCN栅电极具有约80-100μΩ的OMEGA-cm的低电阻，并且可以控制费米能级的变化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式