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    • 12. 发明申请
    • IMAGING DEVICE
    • 成像装置
    • US20110115971A1
    • 2011-05-19
    • US13054183
    • 2009-07-16
    • Shinji FuruyaEiji AnnoYuichi SuzukiTomoaki Tsutsumi
    • Shinji FuruyaEiji AnnoYuichi SuzukiTomoaki Tsutsumi
    • H04N5/225
    • G03B15/05G03B7/08G03B2215/05H04N5/2354H04N5/243H04N5/343H04N5/351
    • The present invention provides an image capture device that can omit calculating a pulse signal that should otherwise be used to get a flash fired during a flash-ON sequential shooting operation.An image capture device includes: an image capturing section configured to capture a subject's image; a flashing section configured to store electricity and emitting flash light using the electricity; a power supply configured to supply the electricity; and a control section configured to control the supply of the electricity to the flashing section. If the flashing section performs preliminary flashing and main flashing sequentially, the control section supplies no electricity to the flashing section after the preliminary flashing is done and before the main flashing is performed for a first time. But after the main flashing is done for the first time, the control section continues to supply, in an interval before a next main flashing, the electricity to the flashing section until the flashing section recovers a quantity of electricity stored there when the main flashing was performed for the first time.
    • 本发明提供了一种图像捕获装置,其可以省略计算在闪光接通顺序拍摄操作期间应该用于获得闪光灯闪光的脉冲信号。 一种图像拍摄装置,包括:图像拍摄部,被配置为拍摄被摄体的图像; 闪光部分,其配置为存储电力并使用电发射闪光灯; 配置为供电的电源; 以及控制部,被配置为控制向闪光部供电。 如果闪烁部分依次进行预备闪烁和主闪烁,则控制部分在初步闪光完成之后以及在首次执行主闪光之前不向闪光部分供电。 但是在主闪电第一次完成之后,控制部分继续在下一次主闪光之前的间隔内向闪电部分供电,直到闪光部分恢复存储在那里的电量,当主闪光是 第一次执行
    • 14. 发明授权
    • Method for determining combination of data for transfer, and combination determining circuit
    • 用于确定用于传送的数据的组合的方法和组合确定电路
    • US07301942B2
    • 2007-11-27
    • US10284383
    • 2002-10-31
    • Shinji FuruyaHirotoshi YamadaNobuyuki Kobayashi
    • Shinji FuruyaHirotoshi YamadaNobuyuki Kobayashi
    • H04Q11/00
    • H04L49/254H04L12/2854H04L29/06
    • A method for determining a combination of data for transfer comprises counting the number of candidates in data for candidates of a data transfer request for each row as the number of candidates at lattice points of a lattice composed of N rows×N columns, searching for a minimum value out of count values equal to or greater than 1, selecting and storing one row showing the minimum value. Regarding the candidates in the selected row, the method also comprises counting the number of candidates in each column where candidates exist, searching for a minimum value, selecting and storing one column, deleting all candidates on the row and the column determined, and repeating these processes until no more candidates exist to determine combinations of rows and columns stored at a point of time when no more candidates exist.
    • 用于确定用于传送的数据的组合的方法包括对作为每行的数据传送请求的候选的候选数的候选数进行计数,作为由N行×N列构成的格子的格点处的候选数,搜索最小值 超出等于或大于1的计数值,选择并存储显示最小值的一行。 关于选择行中的候选者,该方法还包括对候选存在的每个列中的候选数量进行计数,搜索最小值,选择和存储一列,删除所有行上的所有候选和确定的列,并重复这些 过程,直到不存在更多的候选来确定在不存在更多候选的时间点存储的行和列的组合。
    • 18. 发明授权
    • Data processing control system, controller, data processing control method, program, and medium
    • 数据处理控制系统,控制器,数据处理控制方法,程序和介质
    • US06807623B2
    • 2004-10-19
    • US09916050
    • 2001-07-26
    • Manabu MigitaJunji NishikawaIchiro OkabayashiShinji Furuya
    • Manabu MigitaJunji NishikawaIchiro OkabayashiShinji Furuya
    • G06F1100
    • G06F9/52G06F3/0613G06F3/0659G06F3/0689G06F9/4843G06F9/5011
    • A data processing control system has a controller wherein the controller (1) sends every received instruction to the plurality of data processing devices until the number of instructions being executed or waiting to be executed by the plurality of data processing devices reaches a predetermined number, (2) does not send any received instructions to the plurality of data processing devices but holds the received instructions in a queue once the number of instructions being executed or waiting to be executed by the plurality of data processing devices has reached the predetermined number, and (3) when the number of instructions being executed or waiting to be executed by the plurality of data processing devices has become zero by completing the execution thereof, starts sending the queued instructions in sequence to the plurality of data processing devices, and continues to send the queued instructions or every newly received instruction to the plurality of data processing devices until the number of instructions being executed or waiting to be executed by the plurality of data processing devices reaches the predetermined number.
    • 数据处理控制系统具有控制器,其中控制器(1)将每个接收到的指令发送到多个数据处理设备,直到被多个数据处理设备执行或等待执行的指令的数量达到预定数量( 一旦所执行的等待执行的指令的数目已经达到预定数量,并且(2)不向所述多个数据处理装置发送任何接收的指令,而是将所接收的指令保持在队列中,并且 3)当由多个数据处理装置执行或等待执行的指令数量通过完成其执行而变为零时,开始按顺序向多个数据处理装置发送排队的指令,并且继续发送 排队的指令或每个新接收的指令到多个数据处理设备,直到 正在执行或等待由多个数据处理装置执行的指令的数量达到预定数量。
    • 19. 发明授权
    • Data transfer apparatus with improved throughput due to reduced
processing overhead in interrupt process
    • 数据传输设备由于中断处理中的处理开销减少而具有提高的吞吐量
    • US6098121A
    • 2000-08-01
    • US984429
    • 1997-12-03
    • Shinji Furuya
    • Shinji Furuya
    • G06F13/28G06F13/12
    • G06F13/28
    • A data transfer apparatus is provided for transferring data with a DMA method between a plurality of disk apparatuses and a memory using a DMA command table. A processor generates the DMA command table composed of an array of the DMA commands which are each composed of an address (starting address) of the data area and a size of data to be transferred. A disk access unit transfers data between the disk apparatuses and the memory using the DMA command table. When it is judged that the disk apparatus currently transferring data has temporarily released the bus use right, the processor, concurrently in preparation for the resumption of the data transfer, updates the DMA command table by deleting DMA commands having been executed and adding new DMA commands. This eliminates or reduces the generation of the table update interrupt.
    • 提供一种数据传送装置,用于使用DMA命令表在多个盘装置和存储器之间使用DMA方法传送数据。 处理器产生由DMA命令阵列组成的DMA命令表,DMA命令阵列由数据区的地址(起始地址)和要传送的数据的大小组成。 磁盘访问单元使用DMA命令表在盘装置和存储器之间传送数据。 当判断当前正在传送数据的磁盘装置暂时释放总线使用权时,处理器同时准备恢复数据传输,通过删除已经执行的DMA命令并添加新的DMA命令来更新DMA命令表 。 这消除或减少了表更新中断的生成。