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11. 发明授权

US07842585B2 Method to form a photovoltaic cell comprising a thin lamina 有权
标题翻译：形成包括薄层的光伏电池的方法
公开(公告)号：US07842585B2
公开(公告)日：2010-11-30
申请号：US12208392
申请日：2008-09-11
申请人： Srinivasan Sivaram , Aditya Agarwal , S. Brad Herner , Christopher J. Petti
发明人： Srinivasan Sivaram , Aditya Agarwal , S. Brad Herner , Christopher J. Petti
IPC分类号： H01L21/00
CPC分类号： H01L31/022425 , H01L31/0682 , H01L31/0747 , H01L31/1804 , H01L31/1892 , Y02E10/547 , Y02P70/521
摘要： A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only.
摘要翻译：通过在诸如半导体晶片的施主体的表面下方注入气体离子形成非常薄的光伏电池。离子注入限定了解理面，随后的步骤在切割平面处从晶片剥离薄层。光伏电池，或光伏电池的基极或发射极的全部或一部分形成在层内。在优选实施例中，在切割步骤之前将晶片固定到接收器。电接触可以形成在层的两个表面上，或仅形成在一个表面上。

12. 发明授权

US07838350B2 Bottom-gate sonos-type cell having a silicide gate 有权
标题翻译：具有硅化物栅极的底栅超声波型电池
公开(公告)号：US07838350B2
公开(公告)日：2010-11-23
申请号：US11931586
申请日：2007-10-31
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/84 , H01L21/8247
CPC分类号： H01L27/11568 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11578 , H01L27/1203 , Y10S438/954
摘要： A bottom-gate thin film transistor having a silicide gate is described. This transistor is advantageously formed as SONOS-type nonvolatile memory cell, and methods are described to efficiently and robustly form a monolithic three dimensional memory array of such cells. The fabrication methods described avoid photolithography over topography and difficult stack etches of prior art monolithic three dimensional memory arrays of charge storage devices. The use of a silicide gate rather than a polysilicon gate allows increased capacitance across the gate oxide.
摘要翻译：描述了具有硅化物栅极的底栅薄膜晶体管。该晶体管有利地形成为SONOS型非易失性存储单元，并且描述了有效且鲁棒地形成这种单元的单片三维存储器阵列的方法。所描述的制造方法避免了对现有技术的电荷存储装置的单片三维存储阵列的地形和难以堆叠蚀刻的光刻。使用硅化物栅极而不是多晶硅栅极允许跨越栅极氧化物的电容增加。

13. 发明授权

US07830697B2 High forward current diodes for reverse write 3D cell 有权
标题翻译：用于反向写入3D电池的高正向电流二极管
公开(公告)号：US07830697B2
公开(公告)日：2010-11-09
申请号：US11819078
申请日：2007-06-25
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： G11C11/00 , G11C11/14
CPC分类号： H01L27/1021 , G11C11/5692 , G11C13/003 , G11C13/0069 , G11C17/16 , G11C17/165 , G11C2013/009 , G11C2213/33 , G11C2213/71 , G11C2213/72 , H01L27/101
摘要： A nonvolatile memory device includes at least one memory cell which comprises a diode and a metal oxide antifuse dielectric layer, and a first electrode and a second electrode electrically contacting the at least one memory cell. In use, the diode acts as a read/write element of the memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.
摘要翻译：非易失性存储器件包括至少一个存储单元，其包括二极管和金属氧化物反熔丝电介质层，以及第一电极和与该至少一个存储单元电接触的第二电极。在使用中，响应于施加的偏压，二极管通过从第一电阻率状态切换到不同于第一电阻率状态的第二电阻率状态来充当存储单元的读/写元件。

14. 发明授权

US07800933B2 Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance 有权
标题翻译：一种用于使用具有可调整电阻的可切换半导体存储元件的存储单元的方法
公开(公告)号：US07800933B2
公开(公告)日：2010-09-21
申请号：US11496986
申请日：2006-07-31
申请人： Tanmay Kumar , S. Brad Herner , Roy E Scheuerlein , Christopher J Petti
发明人： Tanmay Kumar , S. Brad Herner , Roy E Scheuerlein , Christopher J Petti
IPC分类号： G11C11/00 , G11C11/36
CPC分类号： G11C11/5692 , G11C13/0069 , G11C17/14 , G11C17/165 , G11C2013/0073 , H01L27/101
摘要： A nonvolatile memory cell comprising a diode formed of semiconductor material can store memory states by changing the resistance of the semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) In preferred embodiments, set pulses are applied with the diode under forward bias, while reset pulses are applied with the diode in reverse bias. By switching resistivity of the semiconductor material of the diode, a memory cell can be either one-time programmable or rewriteable, and can achieve two, three, four, or more distinct data states.
摘要翻译：包括由半导体材料形成的二极管的非易失性存储单元可以通过施加设置脉冲（降低电阻）或复位脉冲（增加电阻）来改变半导体材料的电阻来存储存储器状态。在优选实施例中，施加设定脉冲二极管在正向偏置下，而复位脉冲以二极管反向施加。通过切换二极管的半导体材料的电阻率，存储器单元可以是一次性可编程的或可重写的，并且可以实现两个，三个，四个或更多个不同的数据状态。

15. 发明申请

US20100181657A1 NONVOLATILE MEMORY CELL COMPRISING A REDUCED HEIGHT VERTICAL DIODE 有权
标题翻译：包含降低高度垂直二极管的非易失性存储单元
公开(公告)号：US20100181657A1
公开(公告)日：2010-07-22
申请号：US12481684
申请日：2009-06-10
申请人： S. Brad Herner , Steven J. Radigan
发明人： S. Brad Herner , Steven J. Radigan
IPC分类号： H01L29/868 , H01L21/425
CPC分类号： G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/1021 , H01L29/0649 , H01L29/66272 , H01L29/732 , H01L29/868
摘要： A nonvolatile memory cell includes: a rail-shaped first conductor formed at a first height above a substrate; a rail-shaped second conductor formed above the first conductor; and a vertically oriented first pillar comprising a p-i-n first diode; wherein the first pillar is disposed between the second conductor and the first conductor; wherein the first diode comprises an intrinsic or lightly doped region; and wherein the intrinsic or lightly doped region has a first thickness of about 300 angstroms or greater. Numerous additional aspects are provided.
摘要翻译：非易失性存储单元包括：形成在衬底上方的第一高度处的轨道状第一导体; 形成在第一导体上方的轨道形状的第二导体; 以及包括p-i-n第一二极管的垂直取向的第一柱; 其中所述第一柱设置在所述第二导体和所述第一导体之间; 其中所述第一二极管包括固有或轻掺杂区域; 并且其中所述固有或轻掺杂区域具有约300埃或更大的第一厚度。还提供了许多其他方面。

16. 发明授权

US07745312B2 Selective germanium deposition for pillar devices 有权
标题翻译：支柱装置的选择性锗沉积
公开(公告)号：US07745312B2
公开(公告)日：2010-06-29
申请号：US12007780
申请日：2008-01-15
申请人： S. Brad Herner , Christopher J. Petti
发明人： S. Brad Herner , Christopher J. Petti
IPC分类号： H01L21/20
CPC分类号： H01L29/868 , H01L27/1021
摘要： A method of making a pillar device includes providing an insulating layer having an opening, and selectively depositing germanium or germanium rich silicon germanium semiconductor material into the opening to form the pillar device.
摘要翻译：制造柱装置的方法包括提供具有开口的绝缘层，并且将锗或富锗硅锗半导体材料选择性地沉积到开口中以形成柱装置。

17. 发明申请

US20100139755A1 FRONT CONNECTED PHOTOVOLTAIC ASSEMBLY AND ASSOCIATED METHODS 审中-公开
标题翻译：前连接的光伏组件及相关方法
公开(公告)号：US20100139755A1
公开(公告)日：2010-06-10
申请号：US12331376
申请日：2008-12-09
申请人： Christopher J. Petti , Mohamed M. Hilali , S. Brad Herner
发明人： Christopher J. Petti , Mohamed M. Hilali , S. Brad Herner
IPC分类号： H01L31/00 , H01L31/18
CPC分类号： H01L31/02008 , H01L31/022433 , H01L31/0475 , H01L31/0508 , H01L31/0747 , H01L31/1892 , Y02E10/50
摘要： A photovoltaic device is disclosed herein that, in various aspects, includes a conductive layer, and a substantially crystalline lamina with a first surface oriented toward the conductive layer and a second surface oriented away from the conductive layer. The lamina thickness is within the range between about 0.2 microns and about 50 microns. An aperture passes through the lamina from the first surface to the second surface. A connector in electrical communication with the conductive layer is disposed through the aperture. Methods of manufacture of the photovoltaic devise are also disclosed.
摘要翻译：本文公开了一种光电器件，其在各个方面包括导电层，以及具有朝向导电层的第一表面的基本上为晶体的层，以及远离导电层的第二表面。层厚度在约0.2微米至约50微米之间的范围内。孔从第一表面到第二表面通过层。与导电层电连通的连接器穿过孔设置。还公开了光伏设备的制造方法。

18. 发明授权

US07648896B2 Deposited semiconductor structure to minimize n-type dopant diffusion and method of making 有权
标题翻译：沉积半导体结构以使n型掺杂剂扩散最小化和制备方法
公开(公告)号：US07648896B2
公开(公告)日：2010-01-19
申请号：US12181317
申请日：2008-07-28
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/04
CPC分类号： H01L45/08 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L29/161 , H01L29/165 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： In deposited silicon, n-type dopants such as phosphorus and arsenic tend to seek the surface of the silicon, rising as the layer is deposited. When a second undoped or p-doped silicon layer is deposited on n-doped silicon with no n-type dopant provided, a first thickness of this second silicon layer nonetheless tends to include unwanted n-type dopant which has diffused up from lower levels. This surface-seeking behavior diminishes when germanium is alloyed with the silicon. In some devices, it may not be advantageous for the second layer to have significant germanium content. In the present invention, a first heavily n-doped semiconductor layer (preferably at least 10 at % germanium) is deposited, followed by a silicon-germanium capping layer with little or no n-type dopant, followed by a layer with little or no n-type dopant and less than 10 at % germanium. The germanium in the first layer and the capping layer minimizes diffusion of n-type dopant into the germanium-poor layer above.
摘要翻译：在沉积的硅中，诸如磷和砷的n型掺杂剂倾向于寻求硅的表面，随着层的沉积而上升。当在没有提供n型掺杂剂的n掺杂硅上沉积第二未掺杂或p掺杂的硅层时，该第二硅层的第一厚度倾向于包括从较低水平扩散的不期望的n型掺杂剂。当锗与硅合金化时，这种表面寻找行为减弱。在一些设备中，对于第二层可能不是有利的具有显着的锗含量。在本发明中，沉积第一重n掺杂的半导体层（优选至少10原子％的锗），随后是几乎没有或没有n型掺杂剂的硅 - 锗覆盖层，之后是几乎没有或没有 n型掺杂剂和少于10at％的锗。第一层和覆盖层中的锗使n型掺杂剂的扩散最小化到上述的锗贫层中。

19. 发明申请

US20090316468A1 LARGE ARRAY OF UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT 有权
标题翻译：指向具有大电流和均匀电流的上行P-I-N二极管的大阵列
公开(公告)号：US20090316468A1
公开(公告)日：2009-12-24
申请号：US12478481
申请日：2009-06-04
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： G11C17/06 , H01L29/06
CPC分类号： H01L45/122 , B82Y10/00 , G11C13/0007 , G11C17/16 , G11C2213/16 , G11C2213/32 , G11C2213/71 , H01L27/1021 , H01L27/24 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/149 , H01L45/16 , Y10S977/742 , Y10S977/842
摘要： A first memory level includes a first plurality of memory cells that includes every memory cell in the first memory level. Each memory cell includes a vertically oriented p-i-n diode in the form of a pillar that includes a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The first plurality of memory cells includes programmed cells and unprogrammed cells, wherein programmed cells comprise at least half of the first plurality of memory cells. Current flowing through the p-i-n diodes of at least 99 percent of the programmed cells when a voltage between about 1.5 volts and about 3.0 volts is applied between the bottom heavily doped p-type region and the top heavily doped n-type region is at least 1.5 microamps.
摘要翻译：第一存储器级包括包括第一存储器级中的每个存储单元的第一多个存储单元。每个存储单元包括柱形形式的垂直取向的p-i-n二极管，其包括底部重掺杂p型区域，中间固有或轻掺杂区域和顶部重掺杂n型区域。第一组多个存储单元包括编程单元和未编程单元，其中编程单元包括第一多个存储单元的至少一半。在底部重掺杂p型区域和顶部重掺杂n型区域之间施加约1.5伏和约3.0伏特之间的电压时，流经至少99％编程单元的引脚二极管的电流为至少1.5 微电脑

20. 发明申请

US20090197368A1 METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA 有权
标题翻译：形成包含薄层薄膜的光电池的方法
公开(公告)号：US20090197368A1
公开(公告)日：2009-08-06
申请号：US12208392
申请日：2008-09-11
申请人： Srinivasan Sivaram , Aditya Agarwal , S. Brad Herner , Christopher J. Petti
发明人： Srinivasan Sivaram , Aditya Agarwal , S. Brad Herner , Christopher J. Petti
IPC分类号： H01L21/00
CPC分类号： H01L31/022425 , H01L31/0682 , H01L31/0747 , H01L31/1804 , H01L31/1892 , Y02E10/547 , Y02P70/521
摘要： A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only.
摘要翻译：通过在诸如半导体晶片的施主体的表面下方注入气体离子形成非常薄的光伏电池。离子注入限定了解理面，随后的步骤在切割平面处从晶片剥离薄层。光伏电池，或光伏电池的基极或发射极的全部或一部分形成在层内。在优选实施例中，在切割步骤之前将晶片固定到接收器。电接触可以形成在层的两个表面上，或仅形成在一个表面上。

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