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11. 发明授权

US06353266B1 Semiconductor device having improved pad coupled to wiring on semiconductor substrate 失效
标题翻译：具有改善的焊盘的半导体器件耦合到半导体衬底上的布线
公开(公告)号：US06353266B1
公开(公告)日：2002-03-05
申请号：US09572325
申请日：2000-05-18
申请人： Ryuichi Okamura
发明人： Ryuichi Okamura
IPC分类号： H01L2348
CPC分类号： H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05647 , H01L2224/13099 , H01L2924/01004 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/00014
摘要： A semiconductor device includes a semiconductor substrate, a wiring formed on the semiconductor substrate, a cover film formed on the semiconductor substrate and the wiring. The cover film has a through hole to expose the wiring. A pad is formed in the through hole to electrically connect to the wiring without being formed on a top surface of the cover film.
摘要翻译：半导体器件包括半导体衬底，形成在半导体衬底上的布线，形成在半导体衬底上的覆盖膜和布线。盖膜具有通孔以露出布线。在通孔中形成有焊盘以电连接到布线而不形成在覆盖膜的顶表面上。

12. 发明授权

US06175136B1 Method of forming CMOS device with improved lightly doped drain structure 失效
标题翻译：用改进的轻掺杂漏极结构形成CMOS器件的方法
公开(公告)号：US06175136B1
公开(公告)日：2001-01-16
申请号：US09039487
申请日：1998-03-16
申请人： Ryuichi Okamura
发明人： Ryuichi Okamura
IPC分类号： H01L218238
CPC分类号： H01L21/823814 , H01L21/823864
摘要： A semiconductor device has at least a p-channel MOS field effect transistor and at least an n-channel MOS field effect transistor, both of which are integrated on a single semiconductor substrate. The p-channel MOS field effect transistor has at least a first p-type lightly doped diffusion region adjacent to a p-type drain diffusion region. The n-channel MOS field effect transistor has at least a first n-type lightly doped diffusion region adjacent to an n-type drain diffusion region. The first p-type lightly doped diffusion region of the p-channel MOS field effect transistor is shorter in a direction parallel to a channel length direction than a first n-type lightly doped diffusion region of the n-channel MOS field effect transistor.
摘要翻译：半导体器件至少具有p沟道MOS场效应晶体管和至少n沟道MOS场效应晶体管，它们都集成在单个半导体衬底上。 p沟道MOS场效应晶体管具有与p型漏极扩散区域相邻的至少第一p型轻掺杂扩散区域。 n沟道MOS场效应晶体管具有与n型漏极扩散区域相邻的至少第一n型轻掺杂扩散区域。 p沟道MOS场效应晶体管的第一p型轻掺杂扩散区域在平行于沟道长度方向的方向上比n沟道MOS场效应晶体管的第一n型轻掺杂扩散区域短。

13. 发明授权

US6111320A Semiconductor device having a barrier film for preventing penetration of moisture 失效
标题翻译：具有防止水分渗透的阻挡膜的半导体装置
公开(公告)号：US6111320A
公开(公告)日：2000-08-29
申请号：US45875
申请日：1998-03-23
申请人： Ryuichi Okamura
发明人： Ryuichi Okamura
IPC分类号： H01L23/522 , H01L21/768 , H01L23/00 , H01L23/29 , H01L23/48
CPC分类号： H01L23/564 , H01L21/76816 , H01L23/291 , H01L2924/0002
摘要： By assuming a symbol A for the contact depth, B for the diameter of the contact, C for the thickness of the underlay oxide to be formed between the barrier film and the semiconductor substrate, and D for the eave protrusion length of the barrier film the eaves being formed inside the contact when oxide wet etching is performed for removing natural oxide on the silicon and for reducing the contact resistance, the following relation is established,tan.sup.-1 (B/A)
摘要翻译：通过假设接触深度的符号A，接触的直径B，形成在阻挡膜和半导体衬底之间的衬底氧化物的厚度C，阻挡膜的檐突出长度D，在氧化物湿蚀刻用于除去硅上的天然氧化物并降低接触电阻的情况下，在接触部内部形成檐部，形成以下关系：tan-1（B / A）

14. 发明授权

US08546851B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08546851B2
公开(公告)日：2013-10-01
申请号：US13150842
申请日：2011-06-01
申请人： Hiroshi Furuta , Takaaki Kobayashi , Hirofumi Azuhata , Tomoya Morita , Ryuichi Okamura , Toshifumi Takahashi
发明人： Hiroshi Furuta , Takaaki Kobayashi , Hirofumi Azuhata , Tomoya Morita , Ryuichi Okamura , Toshifumi Takahashi
IPC分类号： H01L27/10 , H01L29/76 , H01L29/94 , H01L27/108 , H01L31/119
CPC分类号： H01L27/0207 , H01L27/11807
摘要： In addition to a memory macro region and functional circuit regions on a substrate, a semiconductor integrated circuit device includes a dummy pattern region 40 arranged between the functional circuit regions and between the memory macro region 10 and the functional circuit regions and including a dummy pattern. The dummy pattern has a pattern identical to that of diffusion layers and gate electrodes of a memory cell pattern in a memory cell array region. An area ratio of dummy diffusion layer(s) and dummy gate electrode(s) in the dummy pattern region is equal to or greater than that of the diffusion layers and the gate electrode(s) in the memory cell array region.
摘要翻译：除了存储器宏区域和基板上的功能电路区域之外，半导体集成电路器件还包括布置在功能电路区域之间以及存储器宏区域10和功能电路区域之间并包括虚拟图案的虚设图案区域40。虚设图案具有与存储单元阵列区域中的存储单元图案的扩散层和栅电极相同的图案。虚设图形区域中的虚设扩散层和伪栅电极的面积比等于或大于存储单元阵列区域中的扩散层和栅电极的面积比。

15. 发明授权

US07602064B2 Semiconductor device having an inspection hole striding a boundary 有权
标题翻译：具有跨越边界的检查孔的半导体装置
公开(公告)号：US07602064B2
公开(公告)日：2009-10-13
申请号：US11325482
申请日：2006-01-05
申请人： Masatoshi Watarai , Ryuichi Okamura
发明人： Masatoshi Watarai , Ryuichi Okamura
IPC分类号： H01L23/58
CPC分类号： H01L22/24 , H01L22/34
摘要： The semiconductor device includes a semiconductor substrate, a diffusion layer, an interconnect layer, a contact plug, a contact-inspection hole, a via plug, and a via-inspection hole. Similarly to a contact plug hole, the contact-inspection hole extends from the diffusion layer to the interconnect layer. The opening of the contact-inspection hole on the side of the diffusion layer is disposed across the boundary of the diffusion layer. Also, similarly to a via plug hole, the via-inspection hole extends from an interconnect to an interconnect layer. The opening of the via-inspection hole on the side of the interconnect is disposed across the boundary of the interconnect.
摘要翻译：半导体器件包括半导体衬底，扩散层，互连层，接触插塞，接触检查孔，通孔插头和通孔检查孔。类似于接触塞孔，接触检查孔从扩散层延伸到互连层。扩散层一侧的接触检查孔的开口设置在扩散层的边界的两侧。此外，与通孔塞孔类似，通孔检查孔从互连件延伸到互连层。互连侧面的通孔检查孔的开口跨越互连的边界设置。

16. 发明授权

US06764310B1 Apparatus for simulating ride on vehicle 失效
标题翻译：用于模拟乘坐车辆的装置
公开(公告)号：US06764310B1
公开(公告)日：2004-07-20
申请号：US09667727
申请日：2000-09-22
申请人： Satoru Ichihashi , Masayoshi Kai , Ryuichi Okamura , Kunikazu Negishi , Takeshi Masaki
发明人： Satoru Ichihashi , Masayoshi Kai , Ryuichi Okamura , Kunikazu Negishi , Takeshi Masaki
IPC分类号： G09B1916
CPC分类号： G09B9/058
摘要： An apparatus for simulating a ride on a vehicle has a base, and a simulated vehicle body which is supported on the base with a freedom of two-axis rotation about a rolling axis and a pitching axis. A pair of linear actuators are disposed in a position offset to one side in an axial direction of one of the rolling axis and the pitching axis, e.g., offset to one axial side of the rolling axis relative to the pitching axis. The actuators are disposed symmetrically relative to a plane which crosses the pitching axis at a right angle and which includes an axial line of the rolling axis. A fixing member and a movable member of each of the actuators are coupled to the base and the simulated vehicle body, respectively, through universal joints.
摘要翻译：一种用于模拟在车辆上行驶的装置具有基座和模拟车体，该车体以围绕滚动轴线和俯仰轴线的双轴旋转的自由度被支撑在基座上。一对线性致动器设置在沿着滚动轴线和俯仰轴线之一的轴向偏移的一侧的位置，例如偏移到相对于俯仰轴线的滚动轴线的一个轴向侧。致动器相对于以直角穿过俯仰轴线并且包括滚动轴线的轴线的平面对称地设置。每个致动器的固定构件和可动构件分别通过万向接头联接到基座和模拟车体。

17. 发明授权

US6163057A Field effect transistor with improved source/drain diffusion regions having an extremely small capacitance 失效
标题翻译：场效应晶体管具有改善的源/漏扩散区域，具有极小的电容
公开(公告)号：US6163057A
公开(公告)日：2000-12-19
申请号：US298167
申请日：1999-04-23
申请人： Ryuichi Okamura
发明人： Ryuichi Okamura
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/10 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66575 , H01L21/26513 , H01L29/0653 , H01L29/1083 , H01L29/6659 , H01L29/78654
摘要： The invention provides a diffusion region structure in a semiconductor device wherein the diffusion region is applied with alternating voltages in an operation of the semiconductor device. The structure comprises at least one diffusion region being doped with an impurity of a first conductivity type at a first impurity concentration and also being provided in a semiconductor bulk region doped with an impurity of a second conductivity type at a second impurity concentration lower than the first impurity concentration, and at least a diffusion capacitance reduction layer provided under the diffusion region so as to be in contact with a bottom of the diffusion region. The diffusion capacitance reduction layer may be doped with an impurity of the second conductivity type at a third impurity concentration which is at least lower than the second impurity concentration of the semiconductor bulk region and not lower than zero or may be mode of an insulating material to thereby reduce a capacitance of the diffusion region.
摘要翻译：本发明在半导体器件中提供扩散区结构，其中在半导体器件的操作中，扩散区被施加有交流电压。该结构包括至少一个掺杂有第一导电类型杂质的第一杂质浓度的扩散区，并且还设置在掺杂有第二导电类型的杂质的半导体体区中，第二杂质浓度低于第一杂质浓度杂质浓度，以及设置在扩散区域下方的至少扩散电容降低层，以便与扩散区域的底部接触。扩散电容降低层可以掺杂第二导电类型的杂质，其第三杂质浓度至少低于半导体本体区域的第二杂质浓度并且不低于零，或者可以是绝缘材料的模式从而减小扩散区域的电容。

18. 发明授权

US6011308A Semiconductor device having a barrier film formed to prevent the entry of moisture and method of manufacturing the same 失效
标题翻译：具有形成为防止湿气进入的阻挡膜的半导体装置及其制造方法
公开(公告)号：US6011308A
公开(公告)日：2000-01-04
申请号：US874359
申请日：1997-06-13
申请人： Ryuichi Okamura
发明人： Ryuichi Okamura
IPC分类号： H01L23/522 , H01L21/28 , H01L21/768 , H01L23/00 , H01L23/29 , H01L23/532
CPC分类号： H01L21/76802 , H01L21/76831 , H01L23/291 , H01L23/564 , H01L2924/0002
摘要： A semiconductor device includes a silicon substrate, a first insulating film, a barrier film, a contact hole, a protective film, a barrier metal, and an interconnection metal. A semiconductor element is formed on the silicon substrate. The first insulating film is formed on the silicon substrate. The barrier film is formed on the first insulating film to prevent moisture from externally entering. The contact hole is formed through the barrier film and the insulating film to a depth at which the silicon substrate is exposed. The protective film is formed on the side surface of the contact hole to protect the first insulating film against etching which is performed to remove a spontaneous oxide film formed on a surface of the silicon substrate which is exposed on a bottom surface of the contact hole. The barrier metal is continuously formed on at least the side and bottom surfaces of the contact hole and serves as a buffer conductor. The interconnection metal is buried in the contact hole on which the barrier metal is formed. A semiconductor device manufacturing method is also disclosed.
摘要翻译：半导体器件包括硅衬底，第一绝缘膜，阻挡膜，接触孔，保护膜，阻挡金属和互连金属。在硅衬底上形成半导体元件。第一绝缘膜形成在硅衬底上。阻挡膜形成在第一绝缘膜上，以防止水分从外部进入。接触孔通过阻挡膜和绝缘膜形成到硅衬底暴露的深度。保护膜形成在接触孔的侧表面上，以保护第一绝缘膜不被蚀刻，以除去形成在暴露于接触孔底面的硅衬底表面上的自发氧化膜。阻挡金属连续地形成在接触孔的至少侧面和底面上并用作缓冲导体。互连金属被埋在形成阻挡金属的接触孔中。还公开了半导体器件制造方法。

19. 发明授权

US5801426A Field effect transistor with improved source/drain diffusion regions having an extremely small capacitance 失效
公开(公告)号：US5801426A
公开(公告)日：1998-09-01
申请号：US515941
申请日：1995-08-16
申请人： Ryuichi Okamura
发明人： Ryuichi Okamura
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/10 , H01L29/786 , H01L29/76 , H01L29/74 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66575 , H01L21/26513 , H01L29/0653 , H01L29/1083 , H01L29/6659 , H01L29/78654
摘要： The invention provides a diffusion region structure in a semiconductor device wherein the diffusion region is applied with alternating voltages in an operation of the semiconductor device. The structure comprises at least one diffusion region being doped with an impurity of a first conductivity type at a first impurity concentration and also being provided in a semiconductor bulk region doped with an impurity of a second conductivity type at a second impurity concentration lower than the first impurity concentration, and at least a diffusion capacitance reduction layer provided under the diffusion region so as to be in contact with a bottom of the diffusion region. The diffusion capacitance reduction layer may be doped with an impurity of the second conductivity type at a third impurity concentration which is at least lower than the second impurity concentration of the semiconductor bulk region and not lower than zero or may be mode of an insulating material to thereby reduce a capacitance of the diffusion region.

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