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11. 发明申请

WO2008070138A9 METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN TRANSCEIVER DEVICES 审中-公开
标题翻译：收发器设备之间信道均衡不对称分布的方法和电路
公开(公告)号：WO2008070138A9
公开(公告)日：2009-03-05
申请号：PCT/US2007024948
申请日：2007-12-05
申请人： RAMBUS INC , ZERBE JARED L , ASSADERAGHI FARIBORZ , LEIBOWITZ BRIAN S , LEE HAE-CHANG , REN JIHONG , LIN QI
发明人： ZERBE JARED L , ASSADERAGHI FARIBORZ , LEIBOWITZ BRIAN S , LEE HAE-CHANG , REN JIHONG , LIN QI
IPC分类号： H04L25/03
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane (120-125) that extends between a high-performance integrated circuit (IC) (105) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers (110). The. architecture compensates for performance asymmetry between ICs communicating over a bidirectional lan by instantiating relatively complex transmit (Tx1) and receive (Rx1) equalization cir.cuitry on the higher-performance, side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated (162) based upon the signal response at the receiver of the higher-performance IC (Rx1N).
摘要翻译：收发机体系结构支持在高性能集成电路（IC）（105）和采用较不复杂的发射机和接收机（110）的一个或多个相对低性能的IC之间延伸的信号通道（120-125）上的高速通信。。的。通过在更高性能的通道侧实例化相对复杂的发送（Tx1）和接收（Rx1）均衡电路，体系结构补偿了通过双向lan进行通信的IC之间的性能不对称。基于在更高性能IC（Rx1N）的接收机处的信号响应，高性能IC中的发射和接收均衡滤波器系数都可以自适应地更新（162）。

12. 发明申请

WO2008070138A3 METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN TRANSCEIVER DEVICES 审中-公开
标题翻译：收发器之间通道均衡化的不对称分配方法与电路
公开(公告)号：WO2008070138A3
公开(公告)日：2009-01-15
申请号：PCT/US2007024948
申请日：2007-12-05
申请人： RAMBUS INC , ZERBE JARED L , ASSADERAGHI FARIBORZ , LEIBOWITZ BRIAN S , LEE HAE-CHANG , REN JIHONG , LIN QI
发明人： ZERBE JARED L , ASSADERAGHI FARIBORZ , LEIBOWITZ BRIAN S , LEE HAE-CHANG , REN JIHONG , LIN QI
IPC分类号： H04L25/03
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane (120-125) that extends between a high-performance integrated circuit (IC) (105) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers (110). The. architecture compensates for performance asymmetry between ICs communicating over a bidirectional lan by instantiating relatively complex transmit (Tx1) and receive (Rx1) equalization cir.cuitry on the higher-performance, side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated (162) based upon the signal response at the receiver of the higher-performance IC (Rx1N).
摘要翻译：收发器架构支持在高性能集成电路（IC）（105）和使用较不复杂的发送器和接收器（110）的一个或多个相对低性能的IC之间延伸的信号通道（120-125）上的高速通信，。的。架构通过在车道的较高性能侧实例化相对复杂的发送（Tx1）和接收（Rx1）均衡电路来补偿通过双向LAN通信的IC之间的性能不对称性。基于在高性能IC（Rx1N）的接收机处的信号响应，可以自适应地更新（162）高性能IC中的发射和接收均衡滤波器系数。

13. 发明申请

WO2009003129A2 METHODS AND CIRCUITS FOR ADAPTIVE EQUALIZATION AND CHANNEL CHARACTERIZATION USING LIVE DATA 审中-公开
标题翻译：使用实时数据的自适应均衡和通道特征的方法和电路
公开(公告)号：WO2009003129A2
公开(公告)日：2008-12-31
申请号：PCT/US2008/068409
申请日：2008-06-26
申请人： RAMBUS INC. , LEE, Hae-Chang , REN, Jihong , LEIBOWITZ, Brian S. , MADDEN, Christopher J. , LIN, Qi , ZERBE, Jared L.
发明人： LEE, Hae-Chang , REN, Jihong , LEIBOWITZ, Brian S. , MADDEN, Christopher J. , LIN, Qi , ZERBE, Jared L.
IPC分类号： H04L25/02 , H04L25/03 , H04L1/20
CPC分类号： H04L25/03878 , H04L1/203 , H04L1/205 , H04L25/0224 , H04L25/0242 , H04L25/0264 , H04L25/0272 , H04L25/03012 , H04L25/03343
摘要： A communication system supports high-speed communication over a signal lane that extends between respective transmitting and receiving integrated circuit (IC) devices. One or both of the IC devices includes an equalizer to offset channel characteristics that otherwise impair speed performance. A margining circuit on the receiving IC measures a timing margin of the received signal and adjusts the equalization settings for one or both transmitters to maximize the timing margin. Another embodiment compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex error analysis and adaptation circuitry on the higher-performance side of the lane. The error analysis and adaptation circuitry reduces the error margin of the transmitted signal to introduce bit errors at the receiver, analyzes the bit errors to measure ISI imposed by the channel, and adjusts voltage offsets of the continuous-time signal to compensate for the ISI. In some embodiments the receiver calculates the system response for diagnostics and for computing equalization settings.
摘要翻译：通信系统支持在相应的发射和接收集成电路（IC）设备之间延伸的信号通道上的高速通信。一个或两个IC器件包括均衡器以抵消否则会影响速度性能的通道特性。接收IC上的边缘电路测量接收信号的定时裕度，并调整一个或两个发射机的均衡设置以使定时裕度最大化。另一个实施例通过在车道的较高性能侧实例化相对复杂的误差分析和适配电路来补偿通过双向通道通信的IC之间的性能不对称性。误差分析和自适应电路减少发射信号的误差容限，在接收机引入位错误，分析比特误差以测量信道施加的ISI，并调整连续时间信号的电压补偿以补偿ISI。在一些实施例中，接收机计算用于诊断和计算均衡设置的系统响应。

14. 发明申请

WO2010147608A1 FREQUENCY RESPONSIVE BUS CODING 审中-公开
标题翻译：频率响应总线编码
公开(公告)号：WO2010147608A1
公开(公告)日：2010-12-23
申请号：PCT/US2009/066253
申请日：2009-12-01
申请人： RAMBUS, INC. , OH, Kyung, Suk , WILSON, John , KIM, Joong-Ho , REN, Jihong
发明人： OH, Kyung, Suk , WILSON, John , KIM, Joong-Ho , REN, Jihong
IPC分类号： G06F13/38 , G06F13/40 , G06F9/00
CPC分类号： H04L25/49 , H04L25/4915
摘要： A data system permits bus encoding based on frequency of the bus and the frequency of switching on the bus so as to avoid undesirable frequency conditions such as a resonant condition or interference with other electrical devices. Transmission frequencies along one or more busses are monitored and used to control the encoding process, for example, an encoding process based on data bus inversion (DBI). The use of both a measure of an absolute number of logic levels ("DBI_DC") and a measure of a number of logic level transitions relative to a prior signal ("DBI_AC") provides a measure of control that may be used to compensate for both main and predriver switching noise.
摘要翻译：数据系统允许基于总线的频率和总线上的切换频率的总线编码，以避免不期望的频率条件，例如谐振条件或与其他电气设备的干扰。监视一个或多个总线的传输频率并用于控制编码过程，例如，基于数据总线反转（DBI）的编码处理。使用绝对数量逻辑电平（“DBI_DC”）的度量和相对于先前信号（“DBI_AC”）的逻辑电平转换的数量的度量提供了可用于补偿主要和预先切换的开关噪声。

15. 发明申请

WO2008063431A2 EDGE BASED PARTIAL RESPONSE EQUALIZATION 审中-公开
标题翻译：基于边缘部分响应均衡
公开(公告)号：WO2008063431A2
公开(公告)日：2008-05-29
申请号：PCT/US2007/023600
申请日：2007-11-09
申请人： RAMBUS, INC. , LEIBOWITZ, Brian, S. , LEE, Hae-Chang , REN, Jihong , RATNAYAKE, Ruwan
发明人： LEIBOWITZ, Brian, S. , LEE, Hae-Chang , REN, Jihong , RATNAYAKE, Ruwan
IPC分类号： H04L25/03 , H04L25/497
CPC分类号： H04L25/03057 , G06F13/38 , H04L25/03019 , H04L25/0307 , H04L2025/03369 , H04L2025/03617
摘要： A device (102) implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit (114) that sets the tap weights that are used for adjustment of a received data signal (104). The tap weight adapter circuit (119) sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis (116) may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit (220) generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.
摘要翻译：设备（102）利用基于边缘的部分响应判决反馈均衡来实现数据接收。在一个示例性实施例中，该装置实现一个抽头权重适配器电路（114），其设置用于调整接收到的数据信号（104）的抽头权重。抽头重量适配器电路（119）基于先前确定的数据值设置抽头权重，并使用一组边缘采样器从接收数据信号的边缘分析输入。边缘分析（116）可以包括通过由抽头权重适配器电路确定的抽头权重来调整采样数据信号。时钟发生电路（220）生成边沿时钟信号以控制由边缘采样器组执行的边缘采样。可以根据边缘采样器的信号和由均衡器确定的先前数据值来生成边沿时钟信号。

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