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11. 发明申请

US20090083691A1 SYSTEMS AND TECHNIQUES FOR DEVELOPING HIGH-SPEED STANDARD CELL LIBRARIES 失效
标题翻译：用于开发高速标准单元库的系统和技术
公开(公告)号：US20090083691A1
公开(公告)日：2009-03-26
申请号：US11941286
申请日：2007-11-16
申请人： Paul Penzes
发明人： Paul Penzes
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for providing a high-speed cell library is provided. The method can include, for example, selecting a set of commonly-occurring logic functions. The method can then include obtaining a netlist of area distributions for each of the set of functions. The netlist can be used to synthesize a set of cell libraries wherein an N-diffusion to P-diffusion area allowance is varied among the set of cell libraries. Thereafter, the method may also include comparing a time delay associated with each of the set of cell libraries with a time delay of a library benchmark delay. Based on the comparing, a delay number may be associated with each of the cell libraries. Finally, the cell libraries may be ranked based on the respective delay numbers associated with each of the cell libraries.
摘要翻译：提供了一种用于提供高速单元库的方法。该方法可以包括例如选择一组常见的逻辑功能。该方法然后可以包括获得每组功能的区域分布的网表。网表可以用于合成一组细胞库，其中在扩增区域的N扩散面积允许量在该组细胞库之间是变化的。此后，该方法还可以包括将与该组单元库中的每一个相关联的时间延迟与库基准延迟的时间延迟进行比较。基于比较，延迟数可以与每个单元库相关联。最后，可以基于与每个细胞库相关联的相应的延迟数来对细胞库进行排名。

12. 发明授权

US08575993B2 Integrated circuit with pre-heating for reduced subthreshold leakage 有权
标题翻译：具有预热功能的集成电路可降低亚阈值泄漏
公开(公告)号：US08575993B2
公开(公告)日：2013-11-05
申请号：US13247694
申请日：2011-09-28
申请人： Paul Penzes , Mark Fullerton
发明人： Paul Penzes , Mark Fullerton
IPC分类号： H01L35/00
CPC分类号： H03L7/0802 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3228 , G06F12/14 , G06F21/44 , H01L2924/0002 , H03K3/0315 , H03K3/037 , H03K3/0375 , H03K5/133 , H03K19/01 , H03K2005/00019 , H03K2005/00026 , H03K2005/00058 , H03L7/097 , H03L7/0997 , H01L2924/00
摘要： Certain semiconductor processes provide for the use of multiple different types of transistors with different threshold voltages in a single IC. It can be shown that in certain ones of these semiconductor processes, the speed at which high threshold transistors can operate at decreases with decreasing temperature. Thus, the overall processing speed of an IC that implements high threshold transistors is often limited by the lowest temperature at which the IC is designed (or guaranteed) to properly function. Embodiments of a system and method that overcome this deficiency by “pre-heating” the IC (or at least portions of the IC that implement the high threshold transistors) such that the IC can operate at a frequency (once pre-heated) higher than what would otherwise be possible for a given, minimum temperature at which the IC is designed (or guaranteed) to properly function at are provided.
摘要翻译：某些半导体工艺提供在单个IC中使用具有不同阈值电压的多种不同类型的晶体管。可以看出，在这些半导体工艺中的某些中，高阈值晶体管可以运行的速度随着温度的降低而降低。因此，实现高阈值晶体管的IC的总体处理速度通常受IC设计（或保证）以适当地起作用的最低温度的限制。通过“预热”IC（或实现高阈值晶体管的IC的至少部分）来克服这种缺陷的系统和方法的实施例，使得IC可以以高于在设计（或保证）设计IC（或保证）的给定最低温度下，将提供适当的功能。

13. 发明授权

US08462533B2 System for retaining state data 有权
标题翻译：用于保留状态数据的系统
公开(公告)号：US08462533B2
公开(公告)日：2013-06-11
申请号：US13107591
申请日：2011-05-13
申请人： Paul Penzes
发明人： Paul Penzes
IPC分类号： G11C15/00
CPC分类号： G11C7/10 , G11C5/14 , G11C11/005
摘要： According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles.
摘要翻译：根据一个实施例，用于在断电期间保持集成电路的M位状态数据的系统包括分为M / N组的M个串行扫描触发器，其中M个扫描触发器能够保存/恢复M位的状态数据。每组包含耦合到一系列扫描触发器的合并扫描触发器。每个组中的合并扫描触发器耦合到存储器单元的相应读取端口，并且每个组中的最终扫描触发器耦合到存储器单元的相应写入端口。该系统使存储器单元能够在N个时钟周期内保存M位状态数据。每个合并的扫描触发器具有读选择输入，其能够在N个时钟周期中将状态数据恢复到M个扫描触发器中。

14. 发明申请

US20130043927A1 Integrated Circuit With Pre-Heating For Reduced Subthreshold Leakage 有权
标题翻译：具有预热的集成电路，以减少亚阈值泄漏
公开(公告)号：US20130043927A1
公开(公告)日：2013-02-21
申请号：US13247694
申请日：2011-09-28
申请人： Paul PENZES , Mark Fullerton
发明人： Paul PENZES , Mark Fullerton
IPC分类号： H03K3/011
CPC分类号： H03L7/0802 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3228 , G06F12/14 , G06F21/44 , H01L2924/0002 , H03K3/0315 , H03K3/037 , H03K3/0375 , H03K5/133 , H03K19/01 , H03K2005/00019 , H03K2005/00026 , H03K2005/00058 , H03L7/097 , H03L7/0997 , H01L2924/00
摘要： Certain semiconductor processes provide for the use of multiple different types of transistors with different threshold voltages in a single IC. It can be shown that in certain ones of these semiconductor processes, the speed at which high threshold transistors can operate at decreases with decreasing temperature. Thus, the overall processing speed of an IC that implements high threshold transistors is often limited by the lowest temperature at which the IC is designed (or guaranteed) to properly function. Embodiments of a system and method that overcome this deficiency by “pre-heating” the IC (or at least portions of the IC that implement the high threshold transistors) such that the IC can operate at a frequency (once pre-heated) higher than what would otherwise be possible for a given, minimum temperature at which the IC is designed (or guaranteed) to properly function at are provided.
摘要翻译：某些半导体工艺提供在单个IC中使用具有不同阈值电压的多种不同类型的晶体管。可以看出，在这些半导体工艺中的某些中，高阈值晶体管可以运行的速度随着温度的降低而降低。因此，实现高阈值晶体管的IC的总体处理速度通常受IC设计（或保证）以适当地起作用的最低温度的限制。通过预热IC（或实现高阈值晶体管的IC的至少一部分）来克服这种缺陷的系统和方法的实施例，使得IC可以以比将被加热的频率高（一次预热）否则可能在设计（或保证）IC的给定最低温度下提供正确的功能。

15. 发明授权

US08035419B2 High-speed standard cells designed using a deep-submicron physical effect 有权
标题翻译：使用深亚微米物理效应设计的高速标准电池
公开(公告)号：US08035419B2
公开(公告)日：2011-10-11
申请号：US12651109
申请日：2009-12-31
申请人： Paul Penzes
发明人： Paul Penzes
IPC分类号： H03K19/00
CPC分类号： G06F17/5068 , G06F17/505 , H01L27/0207 , H01L27/11807
摘要： A system comprises signal paths. There are first through n signal paths, n being a positive integer. A critical one of the first through n signal paths is based on being a respective one of the first through n signal paths having a slowest signal propagation and/or a path in which a signal propagates slower than a clock cycle. The critical one of the first through n signal paths comprises a first size of a standard cell including corresponding logic devices. The non-critical ones of the first through n signal paths comprise a second size of a standard cell including corresponding logic devices, the second size being smaller than the first size.
摘要翻译：系统包括信号路径。有n个信号路径，n是正整数。第一至第n信号路径中的关键因素是基于具有最慢信号传播的第一至第n信号路径中的相应一个信号传播和/或信号传播速度慢于时钟周期的路径。第一到第n个信号路径中的关键一个包括包括对应的逻辑设备的标准小区的第一大小。第一至第n信号路径中的非关键信号包括包括对应的逻辑设备的标准单元的第二大小，第二大小小于第一大小。

16. 发明申请

US20110156103A1 Method and System to Reduce Area of Standard Cells 有权
标题翻译：减少标准细胞面积的方法和系统
公开(公告)号：US20110156103A1
公开(公告)日：2011-06-30
申请号：US12650836
申请日：2009-12-31
申请人： Paul PENZES
发明人： Paul PENZES
IPC分类号： H01L27/08 , H01L23/52 , H01L21/82
CPC分类号： H01L27/0207 , H01L27/11807
摘要： A signal routing grid. A first metal layer has wires running in a first direction. A second metal layer, spaced from and substantially parallel to the first metal layer, has wires running in a second direction different to the first direction, such that the wires of the first and second metal layers appear from above or below to form virtual intersections. Vias or contacts are coupled between the first and second metal layers and configured to route signals between the first and second metal layers. Pins are coupled to the first metal layer and configured to provide input signals or receive output signals from a standard cell, the pins being positioned along the wires in the first metal layer so as to be spaced from the virtual intersections.
摘要翻译：信号路由网格。第一金属层具有沿第一方向延伸的导线。与第一金属层间隔开并基本上平行于第一金属层的第二金属层具有沿与第一方向不同的第二方向延伸的线，使得第一和第二金属层的线从上方或下方出现以形成虚拟交叉点。通孔或触点耦合在第一和第二金属层之间并且被配置为在第一和第二金属层之间路由信号。引脚耦合到第一金属层并且被配置为提供输入信号或从标准单元接收输出信号，所述引脚沿着第一金属层中的导线定位成与虚拟交叉点间隔开。

17. 发明授权

US07957172B2 System for retaining state data of an integrated circuit 有权
标题翻译：保持集成电路状态数据的系统
公开(公告)号：US07957172B2
公开(公告)日：2011-06-07
申请号：US11821437
申请日：2007-06-22
申请人： Paul Penzes
发明人： Paul Penzes
IPC分类号： G11C15/00
CPC分类号： G11C7/10 , G11C5/14 , G11C11/005
摘要： According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles.
摘要翻译：根据一个实施例，用于在断电期间保持集成电路的M位状态数据的系统包括分为M / N组的M个串行扫描触发器，其中M个扫描触发器能够保存/恢复M位的状态数据。每组包含耦合到一系列扫描触发器的合并扫描触发器。每个组中的合并扫描触发器耦合到存储器单元的相应读取端口，并且每个组中的最终扫描触发器耦合到存储器单元的相应写入端口。该系统使存储器单元能够在N个时钟周期内保存M位状态数据。每个合并的扫描触发器具有读选择输入，其能够在N个时钟周期中将状态数据恢复到M个扫描触发器中。

18. 发明申请

US20100162187A1 Mixed-Height High Speed Reduced Area Cell Library 失效
标题翻译：混合高度减速区细胞库
公开(公告)号：US20100162187A1
公开(公告)日：2010-06-24
申请号：US12370065
申请日：2009-02-12
申请人： Paul Penzes , Koen Lampaert
发明人： Paul Penzes , Koen Lampaert
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/0207 , H01L27/11807
摘要： A mixed-height cell library for designing integrated circuits is provided. The mixed-height cell library includes a first plurality of cells having a first track height and a second plurality of cells having a second track height that are configured to be coupled to the first plurality of cells at respective power and ground rail lines. A method for mixed-height cell placement and optimization is also provided. The method comprises abutting cells of different track heights to form a plurality of rows of cells by coupling power and ground rails of the cells at a secondary layer that is different from a primary layer that is used to connect active material and determining whether re-ordering cells within rows allows for further compaction of adjacent rows. The method further comprises re-ordering cells within rows so to allow for further compaction of adjacent rows. The method also includes the steps of splitting rows vertically to minimize the distance between the split rows.
摘要翻译：提供了用于设计集成电路的混合高度单元库。混合高度单元库包括具有第一轨道高度的第一多个单元和具有第二轨道高度的第二多个单元，其被配置为在相应的电源和地面轨线处耦合到第一多个单元。还提供了一种混合高度单元放置和优化的方法。该方法包括通过在不同于用于连接活性材料的主层的次级层处耦合电池的功率和接地轨，来形成不同轨道高度的单元以形成多行单元，并确定是否重新排序行内的单元允许相邻行的进一步压缩。该方法还包括重新排序行内的单元，以允许相邻行的进一步压缩。该方法还包括垂直分割行以最小化分割行之间的距离的步骤。

19. 发明申请

US20100148848A1 High speed four-to-one multiplexer 审中-公开
标题翻译：高速四对一多路复用器
公开(公告)号：US20100148848A1
公开(公告)日：2010-06-17
申请号：US12658481
申请日：2010-02-08
申请人： Paul Penzes
发明人： Paul Penzes
IPC分类号： H03K17/00
CPC分类号： H03K17/005
摘要： According to one embodiment, a high speed multiplexer includes a number of data inputs, a number of hot code select inputs, and a final data output. In one embodiment, the high speed multiplexer utilizes a number of intermediate multiplexers, each receiving respective hot code select inputs and providing an intermediate data output. In one embodiment, each intermediate multiplexer has a critical delay path comprising a first NAND gate and a second NAND gate. In one implementation a four-to-one intermediate multiplexer comprises a first two-input NAND gate and a second four-input NAND gate. In one embodiment, a 32-to-1 high speed multiplexer comprises four four-to-one intermediate multiplexers. According to one implementation of this embodiment, the 32-to-1 multiplexer has a critical delay path from any of the data inputs to the final data output comprising a first NAND gate, a second NAND gate, a NOR gate, and a third NAND gate.
摘要翻译：根据一个实施例，高速复用器包括多个数据输入，多个热代码选择输入和最终数据输出。在一个实施例中，高速多路复用器利用多个中间多路复用器，每个接收各自的热码选择输入并提供中间数据输出。在一个实施例中，每个中间多路复用器具有包括第一NAND门和第二NAND门的临界延迟路径。在一个实现中，四对一中间多路复用器包括第一双输入NAND门和第二四输入NAND门。在一个实施例中，32对1高速复用器包括四个四对一中间多路复用器。根据该实施例的一个实现方式，32对1多路复用器具有从任何数据输入到最终数据输出的关键延迟路径，包括第一NAND门，第二NAND门，NOR门和第三NAND 门。

20. 发明申请

US20080316850A1 System for retaining state data of an integrated circuit 有权
标题翻译：用于保持集成电路的状态数据的系统
公开(公告)号：US20080316850A1
公开(公告)日：2008-12-25
申请号：US11821437
申请日：2007-06-22
申请人： Paul Penzes
发明人： Paul Penzes
IPC分类号： G11C14/00
CPC分类号： G11C7/10 , G11C5/14 , G11C11/005
摘要： According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles.
摘要翻译：根据一个实施例，用于在断电期间保持集成电路的M位状态数据的系统包括分为M / N组的M个串行扫描触发器，其中M个扫描触发器能够保存/恢复M位的状态数据。每组包含耦合到一系列扫描触发器的合并扫描触发器。每个组中的合并扫描触发器耦合到存储器单元的相应读取端口，并且每个组中的最终扫描触发器耦合到存储器单元的相应写入端口。该系统使存储器单元能够在N个时钟周期内保存M位状态数据。每个合并的扫描触发器具有读选择输入，其能够在N个时钟周期中将状态数据恢复到M个扫描触发器中。

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