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11. 发明申请

US20060062060A1 Methods and circuits for programming addresses of failed memory cells in a memory device 失效
标题翻译：用于编程存储器件中的故障存储器单元的地址的方法和电路
公开(公告)号：US20060062060A1
公开(公告)日：2006-03-23
申请号：US11229918
申请日：2005-09-19
申请人： Young-sun Min , Nam-jong Kim , Jong-hyun Choi
发明人： Young-sun Min , Nam-jong Kim , Jong-hyun Choi
IPC分类号： G11C29/00
CPC分类号： G11C29/82 , G11C17/18
摘要： A method of programming addresses of failed memory locations in a memory device can be provided by generating a plurality of fail address signals corresponding to a plurality of addresses of failed memory locations in the memory device and then programming the plurality of addresses of failed memory locations to programming cells for use by a redundant circuit during read or write operations to the plurality of addresses of failed memory locations.
摘要翻译：可以通过生成与存储器件中的故障存储器位置的多个地址相对应的多个故障地址信号，然后将失败存储器位置的多个地址编程到故障存储器位置的多个地址来对编程单元供读取或写入操作期间冗余电路用于故障存储单元的多个地址。

12. 发明授权

US6154417A Integrated circuit memory devices having synchronous wave pipelining capability and methods of operating same 有权
标题翻译：具有同步波流水线能力的集成电路存储器件及其操作方法
公开(公告)号：US6154417A
公开(公告)日：2000-11-28
申请号：US436938
申请日：1999-11-08
申请人： Nam-Jong Kim
发明人： Nam-Jong Kim
IPC分类号： G11C11/407 , G11C7/10 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C8/00
CPC分类号： G11C7/1051 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C7/1039 , G11C7/1072
摘要： Integrated circuit memory devices having synchronous wave pipelining capability include a memory cell array and circuitry therein that is electrically coupled to the memory cell array and latches read data accessed from the memory cell array during a prior ith cycle of an internal clock signal (PCLK), in-sync with an i+1th cycle of the internal clock signal. This delayed latching of previously accessed read data increases the data latch margin and improves device reliability even if worst case processing conditions are encountered. This latching circuit includes a register that is responsive to a plurality of register input control signals (DLLi) and a pipelined register input control circuit that generates the plurality of register input control signals in response to a column select disable signal (CSLD). The latching circuit also preferably includes a column select control circuit that latches a value of a bank select signal (CAi.sub.-- BANK) when the internal clock signal is in a first logic state and passes the latched value of the bank select signal as the column select disable signal upon transition of the internal clock signal from the first logic state to a second logic state.
摘要翻译：具有同步波流水线能力的集成电路存储器件包括存储单元阵列和其中的电路，其电耦合到存储单元阵列，并且在内部时钟信号（PCLK）的先前第i个周期期间锁存从存储单元阵列访问的读取数据，与内部时钟信号的第i + 1个周期同步。即使遇到最坏的情况处理条件，这种对先前访问的读取数据的延迟锁存也增加了数据锁存余量并提高了器件的可靠性。该锁存电路包括响应于多个寄存器输入控制信号（DLLi）的寄存器和响应于列选择禁止信号（CSLD）产生多个寄存器输入控制信号的流水线寄存器输入控制电路。锁存电路还优选地包括列选择控制电路，其在内部时钟信号处于第一逻辑状态时锁存存储体选择信号（CAi-BANK）的值，并将存储体选择信号的锁存值作为列选择内部时钟信号从第一逻辑状态转换到第二逻辑状态时禁止信号。

13. 发明申请

US20110051533A1 INTERNAL VOLTAGE GENERATOR CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME 有权
标题翻译：内部电压发生器电路和使用其的半导体存储器件
公开(公告)号：US20110051533A1
公开(公告)日：2011-03-03
申请号：US12874299
申请日：2010-09-02
申请人： Young-Hoon Kim , Nam-Jong Kim
发明人： Young-Hoon Kim , Nam-Jong Kim
IPC分类号： G11C5/14 , G05F1/10
CPC分类号： G11C7/12 , G11C5/14
摘要： An internal voltage generator circuit is disclosed. The internal voltage generator circuit includes a comparator configured to compare a first voltage with a reference voltage and to output a comparison signal. The circuit further includes an internal voltage driver configured to receive an external voltage and the comparison signal and to output an internal voltage at an internal voltage output terminal, based on the comparison signal. The circuit further includes a voltage divider circuit including first and second resistor units and a first voltage output terminal between the first and second resistor units, configured to receive the internal voltage, and configured to output the first voltage based on the resistance values of the first and second resistor units, the first and second resistor units connected in series, and the first voltage being output through the first voltage output terminal. The circuit further includes a control signal generator circuit configured to generate at least one resistor control signal for controlling the resistance value of the first resistor unit and at least one resistor control signal for controlling the resistance value of the second resistor unit, on the basis of the comparison signal and a precharge command.
摘要翻译：公开了内部电压发生器电路。内部电压发生器电路包括比较器，其被配置为将第一电压与参考电压进行比较并输出比较信号。电路还包括内部电压驱动器，其被配置为接收外部电压和比较信号，并且基于比较信号输出内部电压输出端子处的内部电压。该电路还包括一个分压器电路，包括第一和第二电阻器单元以及第一和第二电阻器单元之间的第一电压输出端子，其被配置为接收内部电压，并且被配置为基于第一和第二电阻器的电阻值输出第一电压以及第二电阻器单元，第一和第二电阻器单元串联连接，第一电压通过第一电压输出端子输出。该电路还包括一个控制信号发生器电路，该电路被配置为产生用于控制第一电阻器单元的电阻值的至少一个电阻控制信号和用于控制第二电阻器单元的电阻值的至少一个电阻控制信号比较信号和预充电指令。

14. 发明授权

US07499364B2 Multi-port semiconductor memory device and signal input/output method therefor 有权
标题翻译：多端口半导体存储器件及其信号输入/输出方法
公开(公告)号：US07499364B2
公开(公告)日：2009-03-03
申请号：US11466415
申请日：2006-08-22
申请人： Hyo-Joo Ahn , Nam-Jong Kim
发明人： Hyo-Joo Ahn , Nam-Jong Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/1075 , G11C8/16 , G11C29/1201 , G11C29/48
摘要： A multi-port semiconductor memory device and a signal input/output method therefore are provided. In one embodiment, the multi-port semiconductor memory device includes a plurality of different input/output ports and a memory array. The memory array has at least one memory region that is accessed by using different input/output ports. The different input/output ports include a first input/output port through which a first signal is input/output and a second input/output port through which a second signal different from the first signal is input/output. The memory region is divided into a plurality of memory regions. The invention provides effects of reducing the number of test pins and improving test efficiency.
摘要翻译：因此，提供了多端口半导体存储器件和信号输入/输出方法。在一个实施例中，多端口半导体存储器件包括多个不同的输入/输出端口和存储器阵列。存储器阵列具有通过使用不同的输入/输出端口访问的至少一个存储器区域。不同的输入/输出端口包括输入/输出第一信号的第一输入/输出端口和与第一信号不同的第二信号被输入/输出的第二输入/输出端口。存储区域被分成多个存储区域。本发明提供减少测试针数量并提高测试效率的效果。

15. 发明授权

US07408826B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07408826B2
公开(公告)日：2008-08-05
申请号：US11489440
申请日：2006-07-20
申请人： Jong-Hyun Choi , Dong-Il Seo , Nam-Jong Kim
发明人： Jong-Hyun Choi , Dong-Il Seo , Nam-Jong Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , H01L29/785
摘要： A semiconductor memory device that includes a memory cell array having a plurality of memory cells that are connected between a bit line pair, which transfers data to the bit line pair, a precharge circuit for precharging the bit line pair to a precharge voltage level during a precharge period, and one or more bit line sense amplifiers which are connected between the bit line pair and detect a voltage difference of the bit line pair to amplify a level of the bit line pair. The semiconductor memory device includes one or more FINFETs.
摘要翻译：一种半导体存储器件，包括存储单元阵列，该存储单元阵列具有连接在位线对之间的多个存储单元，所述位线对向位线对传送数据;预充电电路，用于在位置线对期间预充电电压电平预充电周期和连接在位线对之间的一个或多个位线读出放大器，并检测位线对的电压差以放大位线对的电平。半导体存储器件包括一个或多个FINFET。

16. 发明授权

US07330384B2 Verifying circuit and method of repairing semiconductor device 有权
标题翻译：验证电路和修复半导体器件的方法
公开(公告)号：US07330384B2
公开(公告)日：2008-02-12
申请号：US11261497
申请日：2005-10-31
申请人： Young-Sun Min , Jong-Hyun Choi , Nam-Jong Kim
发明人： Young-Sun Min , Jong-Hyun Choi , Nam-Jong Kim
IPC分类号： G11C7/00
CPC分类号： G11C29/787 , G11C17/18
摘要： A verifying circuit and a method of repairing a semiconductor device, the verifying circuit of example embodiments may include a first fuse circuit configured to determine whether a first fuse has been programmed, a test signal generating circuit configured to generate a test signal based on a control signal and an output signal from the first fuse circuit, and a second fuse circuit configured to test whether a plurality of second fuses are programmed based on the test signal.
摘要翻译：一种验证电路和修复半导体器件的方法，示例实施例的验证电路可以包括配置为确定第一熔丝是否已被编程的第一熔丝电路，被配置为基于控制产生测试信号的测试信号产生电路信号和来自第一熔丝电路的输出信号，以及第二熔丝电路，被配置为基于测试信号测试多个第二熔丝是否被编程。

17. 发明授权

US07317335B2 Level shifter with low leakage current 失效
标题翻译：电平移位器具有低漏电流
公开(公告)号：US07317335B2
公开(公告)日：2008-01-08
申请号：US11764241
申请日：2007-06-18
申请人： Young-sun Min , Nam-jong Kim
发明人： Young-sun Min , Nam-jong Kim
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03K3/356113
摘要： A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIhigh and VIlow, where VIhigh>VIlow; and a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOhigh and VOlow, where VOhigh>VOlow, wherein VIhigh>VOhigh or VIlow Vcc and VOlow
摘要翻译：电压电平移位电路包括第一级，其接收具有电压电平Vcc和Vss的输入信号，其中Vcc> Vss，并且其输出互补的第一和第二中间信号，其中互补的第一和第二中间信号具有电压电平VI _{高和VI _{低，其中VI高低> VI _{以及第二级，其接收所述第一和第二中间信号，并且输出互补的第一和第二输出信号，其中所述互补的第一和第二输出信号具有电压电平VO高电平和VO < / SUB>，其中VO VO _{低，其中VI高的低低，并且其中VO高/低Vcc和VO低Vss。}}}}

18. 发明申请

US20070153614A1 Method of operating a semiconductor device and the semiconductor device 有权
标题翻译：操作半导体器件和半导体器件的方法
公开(公告)号：US20070153614A1
公开(公告)日：2007-07-05
申请号：US11711615
申请日：2007-02-28
申请人： Seouk-Kyu Choi , Nam-Jong Kim , Il-Man Bae , Jong-Hyun Choi
发明人： Seouk-Kyu Choi , Nam-Jong Kim , Il-Man Bae , Jong-Hyun Choi
IPC分类号： G11C5/14
CPC分类号： G11C11/4085 , G11C7/06 , G11C11/4074 , G11C11/4091 , G11C2207/065 , G11C2207/2227
摘要： In one example embodiment, a speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.
摘要翻译：在一个示例性实施例中，速度电路路径包括根据半导体器件的工作模式，可控制的工作在较慢的，低亚阈值泄漏电流模式或更快，更高的亚阈值泄漏电流模式的逆变器链。非速度电路路径包括用于减小子阈值泄漏电流的逆变器链，而与半导体器件的工作模式无关。

19. 发明授权

US07135913B2 Reference voltage generating circuit for integrated circuit 失效
标题翻译：用于集成电路的基准电压发生电路
公开(公告)号：US07135913B2
公开(公告)日：2006-11-14
申请号：US10964016
申请日：2004-10-13
申请人： Young-Sun Min , Nam-Jong Kim
发明人： Young-Sun Min , Nam-Jong Kim
IPC分类号： G05F3/24 , G05F3/26
CPC分类号： G05F3/30
摘要： A reference voltage generating circuit has a power supply voltage node to which a driving power supply voltage is intermittently applied. The circuit includes; a first current mirror section including a first MOS transistor of a first conductivity type having a source terminal connected to the power supply voltage node and a gate terminal connected to a drain terminal as a reference voltage output node, and a second MOS transistor of the first conductivity type having a gate terminal connected to the gate terminal of the first MOS transistor of the first conductivity type and a source terminal connected to the power supply voltage node; a second current mirror section including a third MOS transistor of a second conductivity type having a drain terminal connected to the reference voltage output node and a source terminal connected to a first current path to which a first resistor and a first diode are serially connected, and a fourth MOS transistor of the second conductivity type having a gate terminal and a drain terminal connected to the gate terminal of the third MOS transistor of the second conductivity type in common and a source terminal connected to the second current path to which a second diode is serially connected; and a charge transporting section connected between the gate terminal of the first MOS transistor of the first conductivity type in the first current mirror section and the gate terminal of the fourth MOS transistor of the second conductivity type in the second current mirror section.
摘要翻译：参考电压产生电路具有间歇地施加驱动电源电压的电源电压节点。电路包括第一电流镜部分，包括具有连接到电源电压节点的源极端子的第一导电类型的第一MOS晶体管和连接到作为参考电压输出节点的漏极端子的栅极端子，以及第一MOS晶体管，导电类型，其栅极端子连接到第一导电类型的第一MOS晶体管的栅极端子和连接到电源电压节点的源极端子; 第二电流镜部分，包括具有连接到参考电压输出节点的漏极端子的第二导电类型的第三MOS晶体管和与第一电阻器和第一二极管串联连接的第一电流通路连接的源极端子;以及第二导电类型的第四MOS晶体管具有栅极端子和漏极端子，其连接到第二导电类型的第三MOS晶体管的栅极端子，以及连接到第二电流路径的源极端子，第二二极管串联; 以及电荷输送部，连接在第一电流镜部中的第一导电型的第一MOS晶体管的栅极端子与第二电流镜部的第二导电型的第四MOS晶体管的栅极端子之间。

20. 发明申请

US20060028245A1 Level shifter with low leakage current 失效
标题翻译：电平移动器具有低漏电流
公开(公告)号：US20060028245A1
公开(公告)日：2006-02-09
申请号：US11020252
申请日：2004-12-27
申请人： Young-Sun Min , Nam-Jong Kim
发明人： Young-Sun Min , Nam-Jong Kim
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/012
摘要： A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIhigh and VIlow where VIhigh>VIlow; and a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOhigh and VOlow, where VOhigh>VOlow, wherein VIhigh>VOhigh or VIlow Vcc and VOlow
摘要翻译：电压电平移位电路包括第一级，其接收具有电压电平Vcc和Vss的输入信号，其中Vcc> Vss，并且其输出互补的第一和第二中间信号，其中互补的第一和第二中间信号具有电压电平VI _{高和VI _{低其中VI高低> VI _{以及第二级，其接收所述第一和第二中间信号，并且输出互补的第一和第二输出信号，其中所述互补的第一和第二输出信号具有电压电平VO高电平和VO < / SUB>，其中VO VO _{低，其中VI高的低低，并且其中VO高/低Vcc和VO低Vss。}}}}

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