专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20120276706A1 DAMASCENE METAL-INSULATOR-METAL (MIM) DEVICE IMPROVED SCALEABILITY 有权
标题翻译：大金属金属绝缘体 - 金属（MIM）器件改进的可扩展性
公开(公告)号：US20120276706A1
公开(公告)日：2012-11-01
申请号：US13529284
申请日：2012-06-21
申请人： Suzette K. PANGRLE , Steven AVANZINO , Sameer HADDAD , Michael VANBUSKIRK , Manuj RATHOR , James XIE , Kevin SONG , Christie MARRIAN , Bryan CHOO , Fei WANG , Jeffery A. SHIELDS
发明人： Suzette K. PANGRLE , Steven AVANZINO , Sameer HADDAD , Michael VANBUSKIRK , Manuj RATHOR , James XIE , Kevin SONG , Christie MARRIAN , Bryan CHOO , Fei WANG , Jeffery A. SHIELDS
IPC分类号： H01L21/02
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675 , H01L45/1683
摘要： A present method of fabricating a memory device includes the steps of providing a dielectric layer;, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body Filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.
摘要翻译：本发明的制造存储器件的方法包括以下步骤：提供电介质层;在电介质层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体填充开口，并在开关体上设置第二导电体。在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。

12. 发明授权

US08232175B2 Damascene metal-insulator-metal (MIM) device with improved scaleability 有权
标题翻译：大马士革金属绝缘体金属（MIM）装置，具有改进的可扩展性
公开(公告)号：US08232175B2
公开(公告)日：2012-07-31
申请号：US11521204
申请日：2006-09-14
申请人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
发明人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
IPC分类号： H01L21/20
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675 , H01L45/1683
摘要： A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.
摘要翻译：制造存储器件的现有方法包括以下步骤：提供电介质层，在介电层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体填充物并且在开关体上设置第二导电体。在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。

13. 发明授权

US07983089B2 Sense amplifier with capacitance-coupled differential sense amplifier 有权
标题翻译：具有电容耦合差动读出放大器的感应放大器
公开(公告)号：US07983089B2
公开(公告)日：2011-07-19
申请号：US12134905
申请日：2008-06-06
申请人： Bruce Lee Morton , Michael VanBuskirk
发明人： Bruce Lee Morton , Michael VanBuskirk
IPC分类号： G11C16/28 , H03F3/45
CPC分类号： G11C7/12 , G11C7/02 , G11C7/062 , G11C7/18 , G11C8/12 , G11C16/0483 , G11C16/26
摘要： During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.
摘要翻译：在第一读取周期的第一部分期间，确定读出放大器的第一输入是在读周期的第一部分期间基于存储单元的状态接收信息，并且确定第一输入处的电导基本相等在第一部分期间到感测放大器的第二输入处的电导。多个NAND串模块连接到存储器件的全局位线，该存储器件包括形成多个NAND串和缓冲器的存储器列。

14. 发明授权

US07781806B2 Optical erase memory structure 有权
标题翻译：光擦除存储器结构
公开(公告)号：US07781806B2
公开(公告)日：2010-08-24
申请号：US12106180
申请日：2008-04-18
申请人： Michael VanBuskirk , Mark McClain
发明人： Michael VanBuskirk , Mark McClain
IPC分类号： H01L27/148
CPC分类号： H01L27/156 , G11C16/18
摘要： A method for providing an optical erase memory structure including: forming a metal-insulator-metal memory cell; positioning a light emitting diode adjacent to the metal-insulator-metal memory cell; and emitting a light emission from the light emitting diode for erasing the metal-insulator-metal memory cell.
摘要翻译：一种用于提供光学擦除存储器结构的方法，包括：形成金属 - 绝缘体 - 金属存储单元; 将发光二极管邻近金属绝缘体金属存储单元定位; 并且从发光二极管发射光，以擦除金属 - 绝缘体 - 金属存储单元。

15. 发明申请

US20090303798A1 MEMORY DEVICE AND METHOD 有权
标题翻译：存储器件和方法
公开(公告)号：US20090303798A1
公开(公告)日：2009-12-10
申请号：US12134905
申请日：2008-06-06
申请人： Bruce Lee Morton , Michael VanBuskirk
发明人： Bruce Lee Morton , Michael VanBuskirk
IPC分类号： G11C16/06 , G11C11/24 , G11C7/06
CPC分类号： G11C7/12 , G11C7/02 , G11C7/062 , G11C7/18 , G11C8/12 , G11C16/0483 , G11C16/26
摘要： During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.
摘要翻译：在第一读取周期的第一部分期间，确定读出放大器的第一输入是在读周期的第一部分期间基于存储单元的状态接收信息，并且确定第一输入处的电导基本相等在第一部分期间到感测放大器的第二输入处的电导。多个NAND串模块连接到存储器件的全局位线，该存储器件包括形成多个NAND串和缓冲器的存储器列。

16. 发明申请

US20080132068A1 Damascene metal-insulator-metal (MIM) device 有权
标题翻译：大马士革金属绝缘子金属（MIM）器件
公开(公告)号：US20080132068A1
公开(公告)日：2008-06-05
申请号：US11633929
申请日：2006-12-05
申请人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
发明人： Suzette K. Pangrle , Steven Avanzino , Sameer Haddad , Michael VanBuskirk , Manuj Rathor , James Xie , Kevin Song , Christie Marrian , Bryan Choo , Fei Wang , Jeffrey A. Shields
IPC分类号： H01L21/44
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/122 , H01L45/1233 , H01L45/146 , H01L45/1666
摘要： The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.
摘要翻译：制造存储器件的本方法包括以下步骤：提供电介质层，在电介质层中提供开口，在电介质层的开口中提供第一导电体，在开口中提供开关体，并提供第二导电体在开口处。

17. 发明授权

US07355886B1 Method of programming, erasing and reading memory cells in a resistive memory array 有权
标题翻译：在电阻式存储器阵列中编程，擦除和读取存储单元的方法
公开(公告)号：US07355886B1
公开(公告)日：2008-04-08
申请号：US11633791
申请日：2006-12-05
申请人： Wei Daisy Cai , Swaroop Kaza , Colin S. Bill , Michael VanBuskirk
发明人： Wei Daisy Cai , Swaroop Kaza , Colin S. Bill , Michael VanBuskirk
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/72
摘要： The present approach is a method of writing (which may be programming or erasing) data to a selected memory cell of a memory array. The array includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells each including a diode and a resistive memory device in series connecting a word line and a bit line, and a plurality of transistors, each having a first and second source/drain terminals and a gate, each transistor having a first source/drain terminal connected to a bit line. In the present method a voltage is applied to a selected word line, and a voltage is applied to the second source/drain terminal of a transistor having its first source/drain terminal connected to a selected bit line. The voltage applied to the selected word line is greater than the voltage applied to the second source/drain terminal of that transistor.
摘要翻译：本方法是将数据写入（其可以是编程或擦除）数据到存储器阵列的选定存储单元的方法。阵列包括多个字线，多个位线，多个存储单元，每个存储单元包括串联连接字线和位线的二极管和电阻存储器件，以及多个晶体管，每个晶体管具有第一和第二源极/漏极端子和栅极，每个晶体管具有连接到位线的第一源极/漏极端子。在本方法中，对所选择的字线施加电压，并且将电压施加到其第一源极/漏极端子连接到选定位线的晶体管的第二源极/漏极端子。施加到所选字线的电压大于施加到该晶体管的第二源极/漏极端子的电压。

18. 发明申请

US20080062739A1 MEMORY ERASE MANAGEMENT SYSTEM 有权
标题翻译：内存删除管理系统
公开(公告)号：US20080062739A1
公开(公告)日：2008-03-13
申请号：US11470958
申请日：2006-09-07
申请人： Colin Bill , Mark McClain , Michael VanBuskirk
发明人： Colin Bill , Mark McClain , Michael VanBuskirk
IPC分类号： G11C7/00 , G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0097 , G11C2013/0076 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/79
摘要： A memory erase management system is provided, including providing a resistive change memory cell, coupling a first line to the resistive change memory cell, coupling a line buffer to the first line, providing a charge storage device coupled to the line buffer, and performing a single pulse erase of the resistive change memory cell by discharging a current from the charge storage device through the resistive change memory cell.
摘要翻译：提供了一种存储器擦除管理系统，包括提供电阻变化存储单元，将第一行耦合到电阻变化存储单元，将行缓冲器耦合到第一行，提供耦合到行缓冲器的电荷存储装置，以及执行通过从电荷存储装置通过电阻变化存储单元放电电流来对电阻变化存储单元进行单次脉冲擦除。

19. 发明申请

US20060104111A1 DIODE ARRAY ARCHITECTURE FOR ADDRESSING NANOSCALE RESISTIVE MEMORY ARRAYS 有权
标题翻译：用于解决纳米电阻记忆阵列的二极体阵列
公开(公告)号：US20060104111A1
公开(公告)日：2006-05-18
申请号：US10990706
申请日：2004-11-17
申请人： Nicholas Tripsas , Colin Bill , Michael VanBuskirk , Matthew Buynoski , Tzu-Ning Fang , Wei Cai , Suzette Pangrle , Steven Avanzino
发明人： Nicholas Tripsas , Colin Bill , Michael VanBuskirk , Matthew Buynoski , Tzu-Ning Fang , Wei Cai , Suzette Pangrle , Steven Avanzino
IPC分类号： G11C11/36
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0007 , G11C2213/56 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/101 , H01L27/1021
摘要： The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor. The first and second diodes have different threshold voltages
摘要翻译：本存储器结构包括第一导体，第二导体，连接到第二导体的电阻性存储单元，连接到电阻存储单元和第一导体的第一二极管，并且从电阻存储单元向前取向所述第一导体和连接到所述电阻性存储器单元和所述第一导体的第二二极管与所述第一二极管并联，并且在从所述电阻存储器单元到所述第一导体的相反方向上定向。第一和第二二极管具有不同的阈值电压

20. 发明授权

US07894243B2 Methods of programming and erasing resistive memory devices 有权
标题翻译：编程和擦除电阻式存储器件的方法
公开(公告)号：US07894243B2
公开(公告)日：2011-02-22
申请号：US11633800
申请日：2006-12-05
申请人： Michael VanBuskirk , Wei Daisy Cai , Colin S. Bill , Yi-Ching Jean Wu
发明人： Michael VanBuskirk , Wei Daisy Cai , Colin S. Bill , Yi-Ching Jean Wu
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/32
摘要： In a first method of writing data to a resistive memory device (i.e. programming or erasing), successive electrical potentials are applied across the resistive memory device, wherein the successive electrical potentials are of increasing duration. In another method of writing data to a resistive memory device (i.e. programming or erasing), an electrical potential is applied across the resistive memory device, and the level of current through the memory device is sensed as the electrical potential is applied. The application of the electrical potential is ended based on a selected level of current through the resistive memory device.
摘要翻译：在将数据写入电阻存储器件（即编程或擦除）的第一种方法中，连续电势被施加在电阻性存储器件上，其中连续的电势具有增加的持续时间。在将数据写入电阻式存储器件（即编程或擦除）的另一种方法中，在电阻性存储器件上施加电势，并且在施加电位时感测通过存储器件的电流。电位的施加基于通过电阻式存储器件的选定电流水平而结束。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式