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    • 11. 发明授权
    • Method and system for HSDPA bit level processor engine
    • HSDPA位级处理器引擎的方法和系统
    • US07668188B2
    • 2010-02-23
    • US11353886
    • 2006-02-14
    • Li Fung ChangMark HahmSimon Baker
    • Li Fung ChangMark HahmSimon Baker
    • H04L12/28H04L12/56
    • H04L1/0071H04L1/0066H04L1/0067H04L1/0075H04L1/08H04L1/1812H04L1/1845H04L2001/0093
    • Methods and systems for processing signals in a communication system are disclosed and may include pipelining processing of a received HSDPA bitstream within a single chip. The pipelining may include calculating a memory address for a current portion of a plurality of information bits in the received HSDPA bitstream, while simultaneously storing on-chip, a portion of the plurality of information bits in the received bitstream that is subsequent to the current portion. A portion of the plurality of information bits in the received HSDPA bitstream that is previous to the current portion may be decoded during the calculating and the storing. The calculation of the memory address for the current portion of the plurality of information bits may be achieved without the use of a buffer. Processing of the plurality of information bits may be partitioned into a functional data processing path and a functional address processing path.
    • 公开了用于在通信系统中处理信号的方法和系统,并且可以包括在单个芯片内接收的HSDPA比特流的流水线处理。 流水线可以包括计算接收的HSDPA比特流中的多个信息比特的当前部分的存储器地址,同时在片上存储接收到的当前部分之后的接收比特流中的多个信息比特的一部分 。 可以在计算和存储期间对接收到的HSDPA比特流中当前部分之前的多个信息比特的一部分进行解码。 可以在不使用缓冲器的情况下实现多个信息比特的当前部分的存储器地址的计算。 多个信息位的处理可以被划分为功能数据处理路径和功能地址处理路径。
    • 12. 发明授权
    • Wireless terminal turbo decoding module supporting packet splitting and decoding
    • 无线终端turbo解码模块支持分组分解和解码
    • US07586931B2
    • 2009-09-08
    • US11779988
    • 2007-07-19
    • Xiaoxin QiuLi Fung ChangHui LuoSrirang Ashok Lovlekar
    • Xiaoxin QiuLi Fung ChangHui LuoSrirang Ashok Lovlekar
    • H04B7/212
    • H04L1/0051H04L1/0054H04L1/0066H04L1/1819H04L1/1845
    • A baseband processing module of a wireless terminal includes a Turbo decoding module. The Turbo decoding module decodes a Turbo code word to produce one or more Media Access Control (MAC) packet(s) carried by the turbo decode word. Each MAC packet includes a MAC packet header and the MAC packet payload, which carries one or more Radio Link Control (RLC) Packet Data Units (PDUs). The Turbo decoding module decodes the MAC packet header to determine boundaries of the PDUs carried in the MAC packet payload. The Turbo decoding module decodes RLC PDU headers and RLC PDU payloads of the RLC PDUs. The Turbo decoding module writes the decoded MAC packet header, the decoded RLC PDU headers, and the decoded RLC PDU payloads to memory in a word-aligned format. The Turbo decoding module may also operate in various other Turbo decoding modes.
    • 无线终端的基带处理模块包括Turbo解码模块。 Turbo解码模块解码Turbo码字以产生由turbo解码字携带的一个或多个媒体访问控制(MAC)分组。 每个MAC分组包括携带一个或多个无线电链路控制(RLC)分组数据单元(PDU)的MAC分组报头和MAC分组有效载荷。 Turbo解码模块对MAC分组报头进行解码,以确定MAC分组负载中承载的PDU的边界。 Turbo解码模块解码RLC PDU的RLC PDU头部和RLC PDU有效载荷。 Turbo解码模块将解码的MAC分组报头,解码的RLC PDU报头和解码的RLC PDU有效载荷以字对齐格式写入存储器。 Turbo解码模块也可以以各种其他Turbo解码模式工作。
    • 15. 发明授权
    • Method and system for audio CODEC voice ADC processing
    • 音频CODEC语音ADC处理方法和系统
    • US07515071B2
    • 2009-04-07
    • US11565591
    • 2006-11-30
    • Hongwei KongLi Fung Chang
    • Hongwei KongLi Fung Chang
    • H03M7/00
    • H03M3/496
    • Methods and systems for audio CODEC voice ADC processing are disclosed. Aspects of one method may include using a decimating filter that may be enabled to generate 13 MHz, 9-level digital output signal from a 26 MHz, 3-level digital input signal. The 13 MHz, 9-level digital output signal may be processed for RF transmission, for audio output to an output device, and/or utilized for testing by a test fixture, for example. The 13 MHz, 9-level digital output signal may be further processed to generate a 6.5 MHz, 33-level digital signal. The 6.5 MHz, 33-level digital signal may be converted to an analog signal, and processed for audio output and/or testing. The 13 MHz, 9-level digital output signal may also be processed to generate a 40 KHz, 17-bit digital signal, which may be communicated to a test equipment or further processed for RF transmission.
    • 公开了用于音频CODEC语音ADC处理的方法和系统。 一种方法的方面可以包括使用可被用于从26MHz 3级数字输入信号产生13MHz的9级数字输出信号的抽取滤波器。 13MHz,9电平数字输出信号可以被处理用于RF传输,用于音频输出到输出设备,和/或用于例如测试夹具的测试。 可以进一步处理13MHz,9电平数字输出信号,以产生一个6.5MHz,33电平的数字信号。 6.5 MHz,33级数字信号可以转换为模拟信号,并进行音频输出和/或测试。 13MHz的9电平数字输出信号也可以被处理以产生40KHz的17位数字信号,该数字信号可传送到测试设备或进一步处理用于RF传输。
    • 18. 发明申请
    • Frequency domain equalizer for dual antenna radio
    • 双天线收音机的频域均衡器
    • US20080075209A1
    • 2008-03-27
    • US11524584
    • 2006-09-21
    • Junqiang LiMark David HahmNelson R. SollenbergerLi Fung Chang
    • Junqiang LiMark David HahmNelson R. SollenbergerLi Fung Chang
    • H04L1/02H04B1/10
    • H04L25/03038H04L25/0204H04L25/0212H04L25/022H04L2025/03426H04L2025/03605
    • A Radio Frequency (RF) receiver includes a RF front end and a baseband processing module coupled to the RF front end that is operable to receive a time domain signal that includes time domain training symbols and time domain data symbols. The baseband processing module includes a channel estimator operable to process the time domain training symbols to produce a time domain channel estimate, a Fast Fourier Transformer operable to convert the time domain channel estimate to the frequency domain to produce a frequency domain channel estimate, a weight calculator operable to produce frequency domain equalizer coefficients based upon the frequency domain channel estimate, an Inverse Fast Fourier Transformer operable to converting the frequency domain equalizer coefficients to the time domain to produce time domain equalizer coefficients, and an equalizer operable to equalize the time domain data symbols using the time domain equalizer coefficients.
    • 射频(RF)接收机包括RF前端和耦合到RF前端的基带处理模块,其可操作以接收包括时域训练符号和时域数据符号的时域信号。 基带处理模块包括信道估计器,其可操作以处理时域训练符号以产生时域信道估计;快速傅立叶变换器,其可操作以将时域信道估计转换为频域以产生频域信道估计,权重 计算器,其可操作以基于频域信道估计产生频域均衡器系数;反傅里叶变换器,其可操作以将频域均衡器系数转换到时域以产生时域均衡器系数;以及均衡器,其可操作以均衡时域数据 符号使用时域均衡器系数。